Prior to growth on simulated device wafers from TIS (i.e., wafers physically similar to actual device wafers but without the necessary implants to function), various experimental runs were completed on blank silicon wafers. The resulting dopant activation rate, crystallinity, and conductance were monitored for a range of target doping concentrations (, , and ), growth temperatures (350, 400, and 450°C), and epitaxial silicon thicknesses (5, 10, 16, and 20 nm). Through these experiments, it was found that in order to achieve sufficient conductance at 10 nm thickness, the target doping level had to be . At a target doping of , it was calculated from the measured conductance that of the doping layer was activated at 450°C. The SIMS study on the sample (see Fig. 7) showed that surface segregation9 is the cause of low dopant activation. To keep more of the dopant in the film, low growth temperatures () are preferred. However, the crystallinity of the epitaxial film was found to degrade significantly below 400°C, making 400°C the optimum growth temperature. Through this initial set of preliminary experiments reported in Table 2, the growth condition for the first batch of simulated device wafers in our next step was chosen to be 10 nm thick MBE at with an Sb growth temperature of 400°C.