Below approximately 40°K, conventional CMOS technologies show radical departures from room temperature behavior and classical theory, confounding attempts to design readout circuits that have desirable and predictable behavior. Though the effects often seem difficult to explain, they are in all cases due to the effects of carrier freezeout. We have extensively investigated the device properties of CMOS PETs at temperatures very close to absolute zero and conducted a series of process optimizations designed to overcome anomalies that dominate the device behavior. The resulting technology has been used to build readouts for very long wavelength extrinsic silicon detectors, including staring arrays of significant complexity (256x256 pixels). Large die sizes (450 mils) have been produced with high yields (in excess of 50 percent) using this process.

Cryogenic spe telescopes such as the Space Infrared Telescope Faility (SIRTF) require large-area focal plane arrays (FPAs) with high sensitivity. This places large demands on readout arrays to simultaneously provide low noiseand high responsivity at low power dissipation. The Hughes Technology Center (HTC) has developed a low-noise 256x256-pixel readout array applicable to the SIRTF visible Fine Guidance Sensor (FGS), short-wavelength infrared array camera (IRAC), and Infrared Spectrometer (IRS). The readout is designed to operate at temperatures below 10 K. The unit cell employs a switched source follower-per-detector design wherein signals are multiplexed onto four outputs while row and column scanners can flexibly address small block portions of the array to conserve power. The readout has recently beenfabricated using the standard cryo-CMOS process developed at Hit specifically for low-temperawre, low-noise operation. The readout can be used with Si PIN, InSb, and Si impurity-band-conduction (IBC) detector arrays.

The Amber Engineering AE 152 readout is a 32-channel multiplexer built as part of the far-infrared focal plane array development effort for the Space Infrared Telescope Facility (SIRTF). The design of the device addresses a number of constraints peculiar to the operation of germanium photoconductors. In particular, the need for a very high level of bias stability is solved by a non-switched operation of the first stage. Additionally, the readout was optimized for the detector capacitance expected of large bulk photoconductors ( 0.7 pF) and for the slow operating speeds anticipated for this astronomical application. Fabricated in a 1 .25 jim C-MOS process, the circuit utilizes a cascode input stage to provide gain at the front end while avoiding the Miller effect. The AE 152 also includes an internal offset correction and a shift register multiplexer for the output. We present test data for this device at a variety of temperatures, and show read noises as low as 8 electrons at a temperature of 77 K

We describe the development of sensitive extrinsic germanium focal plane arrays for the Space Infrared Telescope Facility (SIRTF). The cryogenic telescope of SIRTF will be used for natural-background-limited astronomical observations, an application that requires arrays of far-infrared sensors of unprecedented sensitivity. For the 30 -55 tm wavelength range, we describe the development of monolithic Ge:Be arrays with associated readouts bump-bonded to a common substrate. For the 55 - 120 im wavelength range, we describe arrays based on a 1 x32 building block that can be stacked into fully-filled two-dimensional arrays. We show results from tests of a 3 x 32 demonstration array that operates at the SIRTF performance levels. This array demonstrates solutions to the problems of 1) maintaining the required detector operating temperature ( < 2K ) ; 2) isolating the array from the heat and photon emission of the readout; 3) achieving long absorption paths in the detectors; and 4) maintaining constant detector bias and low noise from the readout amplifier. The array design permits stacking into the full 32x32 format required for SIRTF The array thermally isolates the readout from the detectors to take advantage of the improved electronics noise performance at the elevated temperature of 20 K. We also show designs for improved versions of the array that emphasize manufacturability and the ability to be space qualified

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 5K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

The spectral noise characteristics of Aerojet GaAs n-JFETs have been investigated down to liquid helium temperatures. Voltage noise characterization was performed with the FET in 1) the floating gate mode, 2) the grounded gate mode to determine the lowest noise readings possible and 3) with an extrinsic silicon photodetector at various detector bias voltages, to determine optimum operating conditions. Current noise characterization was measured at the drain in the temperature range 300 to 77 K. Device design and MBE processing are described. Static I-V characterization is done at 300, 77 and 6 K. The measurements indicate that the Aerojet GaAs n-JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered as a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to that of Si MOSFETs operating at liquid helium temperatures, and is equal to the best Si n-JFETs operating at 300 K

Low-frequency, low-noise, low-power cryogenic electronics to read out photodetectors is being investigated for the star-tracking telescope of the Gravity Probe B spacecraft. We report our initial findings from evaluating more than 20 types of GaAs FETs, both commercial and non-commercial, for this application. Most exhibit useable dc characteristics at cryogenic temperatures, although gate leakage and hysteretic effects (presumably due to charge trapping) could be troublesome. Low-frequency noise (based primarily on grounded-gate measurements) at 4 K is '1/f-like' and for the quietest GaAs FETs appears to be at least as low as the lowest noise values reported for Si MOSFETs at 4 K. Further investigation is needed in several areas.

A high-speed 2 x 64 GaAs readout with direct injection input has been demonstrated. The readout was fabricated in E/D MESFET technology and is intended for hybridization to photovoltaic detector arrays, specifically PV HgCdTe, for use at long wavelength infrared (LWIR) backgrounds (greater than 5 x 10 exp 15 photons/sq cm). System-limited data rate of 50 MHz was achieved at reasonable power dissipation of not greater than 125 mW. Enhancement-mode MESFETs in both implanted and heterostructure E/D MESFET structures were observed to have low 1/f noise and high subthreshold ideality. The noise spectral density of superlattice-buffered heterostructure E-MESFETs operating at drain current of 500 nA (nominal tactical LWIR detector current) was typically about 2 micro-V/Hz exp 1/2 at 1 Hz, which is comparable to silicon NMOS. This is lower than needed for background limited IR photodetector focal plane array sensitivity.

Many IR imaging astronomical and defense applications require focal planes that operate at temperatures less than 20 K. The most widely used readout technology is silicon complementary metal oxide semiconductor (Si CMOS). At ultracold temperatures, however, this technology exhibits undesirable features, such as drain overshoot and kink effects due to frozen out impurities. An InP-based heterostructure device process, under development at Hughes Aircraft Company for high-speed applications, is being assessed for ultracold analog focal plane applications. Benefits should include low power dissipation, low 1/f noise, and radiation hardness. Device performance has been demonstrated at 5 K, comparable with room-temperature performance but with none of the debilitating freezeout effects found in Si CMOS. Focal plane readout circuits based on the InP process are being fabricated.

A device that permits combining high impedance semiconducting IR detectors with low impedance superconducting electronics will have significant benefits for IR sensor systems. We report an improved hybrid three-terminal transimpedance amplifier with significant current gain. The TIA consists of a semiconductor diode configured for injection of electrons into a thin base electrode (less than 25 nm) superconductor-insulator-superconductor junction, whose response is read out by low impedance superconductive electronics. We achieved an input dynamic impedance greater than 10 exp 11 Ohms, an output dynamic impedance of approximately 10 micro-Ohms, a current gain of 20 and an effective input noise current less than 10 exp -14 A/sq rt Hz. We operated the TIA in a sensor test bed with an extrinsic silicon IR detector and a superconductive analog-to-digital converter.

We have built and demonstrated an all superconductive digital readout for use in an IR focal plane array sensor. High performance, ultralow power superconductive circuits perform the functions of low noise preamplification and analog to digital conversion. The superconductive readout was tested with a variety of detectors, including InSb, Si:As, and a thin film NbN superconducting detector. Light sources included a HeNe laser (0.6 micron), a CO2 laser (10 microns), and a blackbody (400 to 900 K). In each case, the detector and readout circuitry was assembled into a 2 inch diameter, 6 inch long test package cooled in a single dewar. We demonstrated the functionality of the detector/readout channel from input photons to output digital signal. The superconductive readout reported here used Nb-based circuits operating at 4 K. An NbN squid amplifier and detector have subsequently been demonstrated above 10 K. We discuss the extension of the entire digital readout to operating temperatures above 10 K.

The NOAO's 8-m IR optimized telescope for Mauna Kea and NASA's SIRTF show that from 1 to 200 microns there are a number of unfulfilled needs in readout electronics. These include: extremely low readnoise, less than 10 electrons, stable operation at temperatures as low as 2 K, high well capacity, greater than 1 e 7 electrons, and integration times from 30 msec to over 100 sec. Sensors for adaptive optics systems are required with readnoise less than 10 electrons and response times of 30 msec. They should be highly efficient from 1 to 2.5 microns, but may have small formats. Ground-based imagers at these wavelengths need comparable readnoise but longer integration times, and the largest possible formats are essential. To achieve these goals improved cryogenic MOSFETS are essential and complete cryogenic CMOS circuits are highly desirable. Experimental cryoptimized MFETS promise to exceed the above noise requirements at 77 K and approach the needs at 2 K.

A possible multiplexer design for the focal plane for the Cassini Visible and Infrared Mapping Spectrometer (VIMS) is reviewed. The instrument's requirements for the multiplexed array are summarized. The VIMS instrument has a modest radiation-hardness requirement due to the trajectory and planetary environments in which the instrument will be required to operate. The total ionizing dose hardness requirement is a few tens of kilorads. A thin-gate oxide of a few hundred angstroms thickness is to be used. Field hardness is to be achieved by guard bands or hardened dielectric isolation. The design is argued to meet the low-noise and radiation-hardness required for imaging at Saturn. The design is versatile enough to provide double-correlated and double-uncorrelated sampling, which is accomplished in the signal processing electronics outside the focal plane.

A class AB CMOS output buffer has been designed for use on an IR focal plane array. Given the requirements for power dissipation and load capacitance a class A output, such as a source follower, would be unsuitable. The approach taken uses a class AB amplifier configured as a charge integrator. Thus it converts a charge packet in the focal plane multiplexer to a voltage which is then the output of the focal plane. With a quiescent current of 18 micro-a and a load capacitance of 100 pf, the amplifier has an open loop unity gain bandwidth of 900 khz. Integral nonlinearity is better than .03 percent over 5.5 volts when run with VDD-VSS = 6v.

Attention is given to a bilinear current integrating and multiplexing circuit with 2 x 128 inputs for direct monolithic coupling with TIR PbSnSe photovoltaic sensors which was designed and manufactured in a modified CMOS technology. Due to the low RA product of the detectors, the input circuitry was designed to accumulate and handle large charge packets. Charge reduction techniques such as partition, skimming, and mainly internal oversampling are implemented. The bias voltage of the individual detectors can be adjusted by implementating the switched capacitor network, and by controlling and adjusting the gate voltage of the direct injection stage. In addition to the analog part, the multiplexer chip also contains the digital circuit for generating the readout sequence.

The development of the direct injection unit cell architecture with a direct readout has produced several varieties of high-performance large-area staring arrays. These arrays satisfy almost all foreseeable missile applications. The uniformity, noise, and linearity lend themselves to low-complexity, high-performance missile systems. These readout integrated circuits (ROICs) are demonstrated with InSb over a spectral band of 0.5 to 5.5 um with NE(Delta)T of 17 mK under ambient tactical and low-background space conditions. Hybridization of eighteen 128 x 128 ROICs with LWIR HgCdTe resulted in an average NE(Delta)T of 21 mK. The new EPIC substrates yielded high-performance 256 x 256 LWIR HgCdTe capable of withstanding 2000 thermal cycles. The simple interface requirements of the /ST ROIC coupled with the high yield and extremely high operability show promise for future low-cost commercial IR systems.

Double ion implantation has been used to fabricate buried-channel CCDs that exhibit good charge transfer efficiency at temperatures down to 50 K while retaining large charge storage capacity. Monolithic IR focal plane arrays integrating such CCDs and Ge(x)Si(1-x)/Si heterojunction detectors show good imaging performance in both the 3-5 micron and 8-10 micron IR spectral bands.

A 10 x 132 CMOS/CCD readout has been developed for low background (photon incidence less than 10 exp 12 photons/sq cm s) IR applications requiring fine orthoscan pitch (25 microns), on-chip signal processing including time delay integration (TDI) and correlated double sampling, high sensitivity, and high speed at operating temperatures compatible with passive or thermoelectric coolers. When hybridized to SWIR (2.5 microns) detectors, TDI channel read noise of not greater than 10 e(-) was measured at 145 K operating temperature. This implies a minimum per pixel read noise of about 3 electrons, approaching the goal of about 1 e(-) read noise needed for stringent SWIR applications including NASA's MOI and NGST missions.

Radiation-hardened A/D converters suitable for converting the output of FPA signals in an SDI environment have not been readily available. Hughes developed a 10-bit, 1-MSPS, total-dose and dose-rate hard A/D converter using a proprietary radiation-hardened bulk CMOS process. This paper describes the A/D converter architecture, semiconductor process, and circuit design. Test results show over 1-Mrad(Si) total-dose tolerance and up to 7 x 10 exp 11 rad(Si)/s at 125 C dose rate without latchup. Neutron fluences up to 3 x 10 exp 14 neutrons/sq cm show negligible effects.

It is generally accepted that sensor systems can benefit from some form of on-focal-plane A/D conversion in terms of overall system noise improvement. The issue of whether or not the Delta-Sigma modulation process can be applied to the development of an approach using conventional A/D converters or cryogenic circuit materials is addressed from the standpoint of the scanning focal plane. Each pixel row of the scanning sensor is treated as a continuous analog signal source with a fixed signal bandwidth. By allocating a Delta-Sigma converter per sensor pixel row, theory predicts the oversample rate required to achieve the designed conversion resolution. The Delta-Sigma consists of two major parts. The modulator, which samples the analog input and develops a corresponding digital bit stream, and the digital signal processor, which compresses the bit stream into the Nyquist rate multibit codes and performs noise filtering, are described. Only the modulator needs to be on the focal plane since its output is digital. This reduces the development problem to one of fitting the modulator only into the allocated space and power budget per sensor.

The paper discusses the implementation and analysis of a correlated triple sampling circuit using analog subtractor/integrators. The software and test setup for noise measurements are also described. The correlation circuitry is part of the signal chain for a 256-element InSb line array used in the Visible and Infrared Mapping Spectrometer. Using a focal-plane array (FPA) simulator, system noise measurements of 0.7 DN are obtained. A test setup for FPA/SPE (signal processing electronics) characterization along with noise measurements is demonstrated.

The design, fabrication, and testing of a state-of-the-art, high-throughput on-focal plane IR-image signal processor is described. The processing functions performed are frame differencing and thresholding. The final focal plane array will consist of a 128 x 128-pixel platinum-silicide detector bump-mounted to an on-chip CCD multiplexer. The processor is in a 128-channel parallel-pipeline format. Each channel consists of a pixel regenerator (charge differencer), 128-pixel frame store CCD memory, pixel differencer, second pixel regenerator, thresholder (analog comparator), and digital latch. Four parallel analog outputs and four parallel digital outputs are included. The digital outputs provide a bit map of the image. All analog clock signals (128 KHz, 256 KHz, and 5 MHz) are generated by on-chip TTL-input clock drivers. TTL clock driver inputs are generated off-chip. The technology is low-temperature surface and buried channel CCD/CMOS/indium bump. The design goal was 8-bit resolution at 77 K and 1000 frames/s. Applications include point- or extended-target motion detection with thresholding. Design trade-offs and enhancements (such as on-chip detector gain compensation and a simple window processor) are discussed.

When large-field IR sensors are quite distant from the scene, targets appear as points, so detection is based on their motion, rather than their structure. The appearance of background and clutter bright points, although eventually rejected as nontargets, unnecessarily burdens tracking algorithms. Typical approaches involve eliminating background prior to tracking, or only looking within dynamic search boxes based on previous-frame target observations. This presentation describes a method for distributed predetection of points due to moving targets, in which background points are be automatically rejected, and only those detector returns that are most likely to be from targets are be provided to the tracking algorithm. The paper discusses the retinally inspired concepts behind the proposed method, analytical and empirical evaluations of its performance, and a hardware implementation based on Mead's (1989) analog VLSI circuits, resulting in a fine-grained-parallel architecture suitable for on-focal-plane applications.

This paper describes a fiber optic subsystem currently in use at Kitt Peak National Observatory (KPNO) for linking infrared instruments at the telescope with the remotely located digital signal processor (DSP) in the telescope computer room. This system is capable of transmitting and receiving ten transputer links at full link speed over four optical fibers. Transputers are equipped with bidirectional serial communication links. These links, coupled with a simple processor architecture, make transputers ideal for the embedded controller, state generator, and parallel processing tasks required by modern infrared instruments using large two-dimensional arrays. Communication between transputers separated by a short distance can proceed over wires in the conventional sense but for communication over long distances, such as between subsystems in astronomical instruments, other techniques are needed if the full link speed of 20 Mbits/sec is to be maintained. Fiber optics provides an ideal solution to this problem. It also provides immunity from noisy environments and electrical isolation between subsystems. The problem with using fiber optics with transputers is that the links are asynchronous (synchronization is handled within the receiving transputer) while the fiber optic transmitters and receivers require a clock for encoding and decoding the transmitted data. In this paper we address this problem and provide a solution which satisfies both needs.