This PDF file contains the front matter associated with SPIE Proceedings Volume 9661 including the Title Page, Copyright information, Table of Contents, Foreword, Authors, and Conference Committee listing.

Large-field projection lithography for FPDs has developed gradually since the 90s. The LCD screen technology has remained largely unchanged and incremental development has given us better image quality, larger screen sizes, and above all lower cost per area. Recently new types of mobile devices with very high pixel density and/or OLED displays have given rise to dramatically higher requirem ents on photomask technology. Devices with 600 ppi or m ore need lithography with higher optical resolution and better linewidth control. OLED di splays pose new challenges with high sensitivity to transistor parameters and to capacitive cross-talk. New mask requirements leads to new maskwriter requirements and Mycronic has developed a new generation of large -area mask writers with significantly improved properties. This paper discusses and shows data for the improved writers. Mask production to high er quality stan dards also need metrology to verify the quality and Mycronic has introduced a 2D metrology tool with accuracy adequate for current and future masks. New printing or additive methods of producing disp lays on plastic or metal foil will make low-cost disp lays available. This inexpensive type of disp lays will exist side by side with the photographic quality displays of TVs and mobile devices, which will continue to be a challenge in terms of mask and production quality.

The high-end semiconductor mask fabrication is dominated by e-beam technology. But still more than 50% of all semiconductor masks are produced by laser writers. The current laser writers are based on the same technology that was used 25 years ago. They are reliable and fast but not very economical. Heidelberg Instruments has developed a new economical and fast laser writer based on the latest technologies.

As ArF immersion lithography continues to be extended by adopting multi-patterning techniques, imaging requirements continue to become more stringent ^[1-3]. For multiple patterning based logic devices, the optimal printability is not only driven by the optimization of the optical proximity correction (OPC), but also by complex process factors, such as resist, exposure tool, and mask-related error performance levels. In addition the light source plays a crucial role; it has been widely demonstrated ^[4-8] how changes in the E95 bandwidth can significantly lead to changes in on wafer patterning due image contrast changes. Cymer has developed novel computational and experimental approaches to enable process characterization studies ^[9-11]. Using these techniques, simulations were used to assess how E95 bandwidth changes can erode the CDU budget on ≤ 20 nm logic features. Using the results of these simulations, experimental conditions were defined to study the on wafer impact of light source performance on an imec N10 Logic-type test vehicle via six different Metal 1 Logic features. The imaging metrics used to track patterning response are process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).

Recent industrial results around directed self-assembly (DSA) of block copolymers (BCP) have demonstrated the high potential of this technique [1-2]. The main advantage being cost reduction thanks to a reduced number of lithographic steps. Meanwhile, the associated correction for mask creation must account for the introduction of this new technique, maintaining a high level of accuracy and reliability. In order to create VIA (Vertical Interconnect Layer) layer, graphoepitaxy DSA can be used. The technique relies on the creation of a confinement guides where the BCP can separate into distinct regions and resulting patterns are etched in order to obtain an ordered series of VIA contact. The printing of the guiding pattern requires the use of classical lithography. Optical proximity correction (OPC) is applied to obtain the best suited guiding pattern allowing to match a specific design target.

In this study, an original approach for DSA full chip mask optical proximity correction based on a skeleton representation of a guiding pattern is proposed. The cost function for an OPC process is based on minimizing the Central Placement Error (CPE), defined as the difference between an ideal skeleton target and a generated skeleton from a guiding contour. The high performance of this approach for DSA OPC full chip correction and its ability to minimize variability error on via placement is demonstrated and reinforced by the comparison with a rigorous model. Finally this Skeleton approach is highlighted as an appropriate tool for Design rules definition.

Traditional EUV masks, with absorber on top of the multi-layer (ML) mirror, generally suffer from mask 3D effects: H/V shadowing, best focus shifts through pitch and pattern shifts through focus. These effects reduce the overlapping process window, complicate optical proximity correction and generate overlay errors. With further pitch scaling, these mask 3D effects are expected to become stronger, increasing the need for a compensation strategy. In this study, we have proven by simulations and experiments that alternative mask technologies can lower mask 3D effects and therefore have the potential to improve the imaging of critical EUV layers. We have performed an experimental imaging study of a prototype etched ML mask, which has recently become available. This prototype alternative mask has only half the ML mirror thickness (20 Mo/Si pairs) and contains no absorber material at all. Instead, the ML mirror is etched away to the substrate at the location of the dark features. For this etched ML mask, we have compared the imaging performance for mask 3D related effects to that of a standard EUV mask, using wafer exposures at 0.33 NA. Experimental data are compared to the simulated predictions and the benefits and drawbacks of such an alternative mask are shown. Besides the imaging performance, we will also discuss the manufacturability challenges related to the etched ML mask technology.

Aberration sensitive structures, such as two-bar structures, in general suffer from phase effects. The topography of the mask leads to a phase distribution across the diffraction-orders, and hence the image of a two-bar is potentially also distorted due to the topography, leading to full wafer-CDU being larger than required. The phase across the diffraction orders is dependent on the angle of incidence of the imaging light. For ArF it was found before that optimizing the phase distribution leads to a better process-window. It is of interest to investigate the origin and impact of the phase distribution for EUV imaging, since in this case the phase differences depend even stronger on angle. By using analysis from a double-diffraction model and simulations it is shown how illumination setting and stack properties influence the image. Specifically it is shown that two-bar features have better overlapping process window for thinner absorbers whereas spaces through pitch require a thicker absorber.

EUV sources emit a broad band DUV Out-of-Band (OOB) light, in particular, in the wavelength range 100-400 nm. This can cause additional exposure of EUV resists made that are based on a ArF/KrF resist platform. This DUV light is partially suppressed while travelling through the optical path but a non-negligible part of it reaches wafer level and impacts imaging.

This is important for imaging at the edges of an image field when fields are printed very close to each other on the wafer (so-called butted fields, with zero field to field spacing). DUV light is reflected from the reticle black border (BB) into a neighboring exposure field on the wafer. This results in a CD change at the edges and in the corners of the fields and therefore has an impact on CD uniformity. Experimental CDU results are shown for 16 nm dense lines (DL) and 20 nm isolated spaces (IS) (N7 logic design features) in the fields exposed at 0 mm and 0.5mm distance on the wafer. Areas close to the edge of the image field are important for customer applications as they often contain qualification and monitoring structures; in addition, limited imaging capabilities in this area may result in loss of usable wafer space.

In order to understand and control OOB DUV light, it must be measured in the scanner. DUV measurements are performed in resist using a special OOB reticle coated with Aluminum (Al) having low EUV reflectance and high DUV reflectance. A model for DUV light impact on the imaging is proposed and verified. For this, DUV reflectance data is collected in the wavelengths range 100-400 nm for Al and BB and the ratio of reflectances of these materials is determined for assumed scanner and resist OOB spectra. Also direct BB OOB test is performed on the wafer and compared to Al OOB results. The sensitivity of 16 nm DL and 20 nm IS to OOB light is experimentally determined by means of double exposure test: a wafer with exposed imaging structures undergoes a second flood exposure from a DUV reflective material (Al or BB).

Finally, several OOB mitigation strategies are discussed, in particular, suppression of DUV light in the scanner (~3x improvement), recent successes of DUV suppression for 16 nm imaging resist (~1.8x improvement) and DUV reflectance mitigation in the reticle black border (~3.8x). An overview of OOB test results for multiple NXE systems will be shown including systems with new NXE:3350 optics with improved OOB suppression.

To provide insights into best practices of constructing an OPC recipe that suppresses wafer image rippling, we design versatile fragmentation rules with respect to the model-based resist image. Specifically, by recognizing that rippling effect exists before fragmentation, we conduct a coarse simulation with default engine settings and extract raw ripple sinusoidal components associated with signature geometries along all dimensions. The signal is predominantly optical, hence a good representation of the unfiltered diffraction. By referencing the rippling periodic features, we derive a global solution for fragmentation with full respect to geometrical boundary conditions. The methodology enables us to generate a robust fragmentation solution with minimum trial and error and improve target convergence especially along unfavorable dimensions.

OPC Verification is important to identify the critical wafer hotspots prior to mask fabrication. It helps to identify process limiting structures and possible yield limiters. These hotspots are also used by litho engineers to set up process conditions upfront. OPC Verification generally involves verification done at nominal and process window conditions. The process window conditions take into consideration typical process variations for lithography. In this standard flow, the post CMP topography variation was also lumped into these process variations via focus. But in current technologies especially in higher metal layers, CMP induced topography variation has become a major contributor to limit the overall process window. This results in different best focus for structures with different topography. This gives rises to requirement of OPC Verification flow taking into account these location-specific variations in order to know if the mask data can be used or not. This paper proposes a method to incorporate the topography induced focus shift into the OPC Verification flow. OPC Verification checks are performed at the new nominal and Process window conditions to identify the real hotspots seen on wafer. Results are shown where the highlighted hotspots with the proposed new flow correlate better with wafer results. Runtime was also taken into consideration when the flow was developed. Experiments on various products show better accuracy with minimal runtime impact.

The most exciting and continuous debate in our industry is how long Moore’s law will continue, and tightly connected to this is the discussion on when EUV Lithography will be introduced in microchip mass manufacturing. In this review paper, we analyze and extrapolate Moore’s law based on critical design pitches for Logic and Memory devices. We will focus in more detail on an aggressive option for the 7nm Logic node based on an extrapolation in accordance with Moore’s law. For this node, we will discuss and compare all-immersion vs immersion-EUV based litho manufacturing costs, complexity and restrictions and consolidate field expert statements on device performance tradeoffs. We will conclude with an outlook on the affordability of shrink based on node-on-node CapEx projections. Based on interactions with our customers and peers, we project Moore’s law to continue in the 2020s, and we predict that shrink will remain profitable. Manufacturing cost and complexity will be mitigated by the introduction of EUV lithography. The recent progress in EUV productivity will ensure cost effectiveness of EUV-based designs, creating a “sweet spot” for EUV introduction at the 7nm node.

While the 10nm logic node is getting ready for High Volume Manufacturing, the industry has started to make the technology and design choices for the 7nm node. An important question for the industry is whether to make an irreversible choice for EUV, or to keep both EUV and ArFi multi-patterning as options. In the former case, it implies that the design rules of several critical layers will be such that the resulting 2D patterns can only be reliably imaged using EUV. In the latter case, the design rules result in 1D like patterns which are compatible with ArFi multiple patterning, either by application of cut-/block masks or by direct print. In this presentation we will compare the various patterning options by means of an edge placement error (EPE) based performance analysis. We will explain the advantages and considerations of an EPE budget compared to a traditional critical dimension uniformity (CDU) budget. The EPE analysis will be applied on imaging results using critical building blocks or constructs taken from 1D and 2D logic designs. These include cut mask, line-ends and 2D patterns. The trade-offs between the different designs in terms of imaging performance will be evaluated, showing the minimum pitch and tip-to-tip that can be supported based on the required EPE budget. In the end we will summarize the trade-offs for the N7 design choices based on the EPE assessment.

The work presented here describes the analysis of problems of the realization of alternative wavefront measurement methods for lithography exposure machines. The measurement method that is introduced is a redesign of a conventional Shack-Hartmann wavefront sensor and was based on the usage of a single pinhole and the lithography machine itself. Such a redesign is useful because it increases the degrees of freedom. Therefore, there is more freedom to analyze the problems of designing and planning measurements. A group of hardware prototypes under laboratory conditions with the required angular and lateral resolution were realized. For the approximation of the measurement results, numerical simulations are implemented using the Monte-Carlo method in order to statistically design the experiments themselves.

Extreme Ultraviolet (EUV) Lithography is still viewed as the most promising approach for maintaining the pace of Moore's Law. Recent real achievements in EUV Lithography (EUVL) have encouraged semiconductor manufacturers to reconsider their road maps. One of the principal challenges in the ongoing EUVL implementation for high volume manufacturing (HVM) is the availability of necessary clean at wavelength metrology tools. EUV Tech is the world's leading manufacturer of at-wavelength EUV metrology equipment. Founded in 1997, EUV Tech has pioneered the development of several stand-alone inspection, metrology, and calibration tools for EUV lithographic applications that can be operated in a clean room environment on the floor of a fab. In this paper, EUV Tech’s R&D program to minimize particle adders in our EUV Reflectometer along with the ongoing effort to enhance the reflectivity and wavelength, precision and accuracy required to qualify the EUV masks for HVM. In addition to preliminary results from our stand alone EUV Scatterometer developed to characterize the phase roughness of a EUV mask and the introduction of EUV Tech’s Pellicle test suite for testing EUV pellicles.

The adhesion promoter Hexamethyldisilazane (HMDS) plays a crucial role in i-line lithography. According to HMDS deposition forms, a hydrophobic surface defines upwardly directed, non-polar trimethysilyl groups. This condition is of particular importance for wet chemical development and subsequent wet chemical etching processes, because the defined hydrophobic surface prevents water from creeping beneath the resist mask. Undesirable effects, such as (partial) loss of the resist structure or under etching can be prevented. Currently, a common and suitable method to control the success of HMDS deposition is the contact angle measurement. There, a drop of water is applied to the substrate and the contact angle / wetting angle is measured. As a result, conclusions can be drawn about the HMDS process. Unfortunately, however, this simple to implement measurement method raises some problems. The measurement is extremely dependent on the substrate, wherein the measurement results vary greatly. A possible reason for this is the different surface properties of the wafers which are due to adsorbate films. Typically, a contact angle measurement is performed just after the HMDS deposition. A difference between pre- and post-measurement cannot be determined. A deviation of the contact angle can be caused by either an insufficient HMDS seeding, or just as well by other, unknown surface properties. The studies presented here were performed with the measuring system ChemetriQ 5000 from Qcept Technologies. This measurement system was originally developed for Inspection on non-visible defects on the wafer level. It is able to detect differences of work functions as a result of surface coverage by thin film / adsorbate, materials or residues. The change in the surface work function due to the generated adsorbate layer during the HMDS deposition is determined by the measuring system by means of a difference between pre- and post-measurement.

The decreasing size and increasing complexity of photomask features, driven by the push to ever smaller technology nodes, places more and more challenges on the mask house, particularly in terms of yield management and cost reduction. Particularly challenging for mask shops is the inspection, repair and review cycle which requires more time and skill from operators due to the higher number of masks required per technology node and larger nuisance defect counts. While the measurement throughput of the AIMS™ platform has been improved in order to keep pace with these trends, the analysis of aerial images has seen little advancement and remains largely a manual process. This manual analysis of aerial images is time consuming, dependent on the skill level of the operator and significantly contributes to the overall mask manufacturing process flow.

AutoAnalysis, the first application available for the FAVOR® platform, offers a solution to these problems by providing fully automated analysis of AIMS™ aerial images. Direct communication with the AIMS™ system allows automated data transfer and analysis parallel to the measurements. User defined report templates allow the relevant data to be output in a manner that can be tailored to various internal needs and support the requests of your customers. Productivity is significantly improved due to the fast analysis, operator time is saved and made available for other tasks and reliability is no longer a concern as the most defective region is always and consistently captured. In this paper the concept and approach of AutoAnalysis will be presented as well as an update to the status of the project. The benefits arising from the use of AutoAnalysis will be discussed in more detail and a study will be performed in order to demonstrate.

YieldStar (YS) is an ASML-built scatterometry tool with well-established capability to measure wafer Critical Dimension (CD), Overlay and Focus. In a feasibility study, the application range of YS was extended to measure CD patterns in EUV reticles (absorber CD, height, Side Wall Angle-SWA). The measured data compared well with the available data from CD-SEM and AFM. Further the YS measured data was used to mathematically separate the reticle induced fingerprint from the scanner fingerprint.

The new device architectures and materials being introduced for sub-10nm manufacturing, combined with the complexity of multiple patterning and the need for improved hotspot detection strategies, have pushed current wafer inspection technologies to their limits. In parallel, gaps in mask inspection capability are growing as new generations of mask technologies are developed to support these sub-10nm wafer manufacturing requirements. In particular, the challenges associated with nanoimprint and extreme ultraviolet (EUV) mask inspection require new strategies that enable fast inspection at high sensitivity. The tradeoffs between sensitivity and throughput for optical and e-beam inspection are well understood. Optical inspection offers the highest throughput and is the current workhorse of the industry for both wafer and mask inspection. E-beam inspection offers the highest sensitivity but has historically lacked the throughput required for widespread adoption in the manufacturing environment. It is unlikely that continued incremental improvements to either technology will meet tomorrow’s requirements, and therefore a new inspection technology approach is required; one that combines the high-throughput performance of optical with the high-sensitivity capabilities of e-beam inspection.

To support the industry in meeting these challenges SUNY Poly SEMATECH has evaluated disruptive technologies that can meet the requirements for high volume manufacturing (HVM), for both the wafer fab [1] and the mask shop. Highspeed massively parallel e-beam defect inspection has been identified as the leading candidate for addressing the key gaps limiting today’s patterned defect inspection techniques. As of late 2014 SUNY Poly SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for defect inspection. A champion approach has been identified based on a multibeam technology from Carl Zeiss. This paper includes a discussion on the need for high-speed e-beam inspection and then provides initial imaging results from EUV masks and wafers from 61 and 91 beam demonstration systems. Progress towards high resolution and consistent intentional defect arrays (IDA) is also shown.

For C040 technology and below, photolithographic depth of focus control and dispersion improvement is essential to secure product functionality. Critical 193nm immersion layers present initial focus process windows close to machine control capability. For previous technologies, the standard scanner sensor (Level sensor - LS) was used to map wafer topology and expose the wafer at the right Focus. Such optical embedded metrology, based on light reflection, suffers from reading issues that cannot be neglected anymore. Metrology errors are correlated to inspected product area for which material types and densities change, and so optical properties are not constant. Various optical phenomena occur across the product field during wafer inspection and have an effect on the quality and position of the reflected light. This can result in incorrect heights being recorded and exposures possibly being done out of focus. Focus inaccuracy associated to aggressive process windows on critical layers will directly impact product realization and therefore functionality and yield. ASML has introduced an air gauge sensor to complement the optical level sensor and lead to optimal topology metrology. The use of this new sensor is managed by the AGILE (Air Gauge Improved process LEveling) application. This measurement with no optical dependency will correct for optical inaccuracy of level sensor, and so improve best focus dispersion across the product. Due to the fact that stack complexity is more and more important through process steps flow, optical perturbation of standard Level sensor metrology is increasing and is becoming maximum for metallization layers. For these reasons AGILE feature implementation was first considered for contact and all metal layers. Another key point is that standard metrology will be sensitive to layer and reticle/product density. The gain of Agile will be enhanced for multiple product contribution mask and for complex System on Chip. Into ST context (High mix logic Fab) in term of product and technology portfolio AGILE corrects for up to 120nm of product topography error on process layer with less than 50nm depth of focus Based on tool functionalities delivered by ASML and on high volume manufacturing requirement, AGILE integration is a real challenge. Regarding ST requirements “Automatic AGILE” functionality developed by ASML was not a turnkey solution and a dedicated functionality was needed. A “ST homemade AGILE integration” has been fully developed and implemented within ASML and ST constraints. This paper describes this integration in our Advanced Process Control platform (APC).

The 14nm node designs is getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. One of the most critical processes is the contact patterning due to the very aggressive design rules and the process window which becomes quickly limited. Despite the large number of RET applied, some hotspot configurations remain challenging. It becomes increasingly challenging to achieve sufficient process windows around the hot spots just using conventional process such as OPC and rule-based SRAF insertion. Although, it might be desirable to apply Inverse Lithography Technique (ILT) on all hot spots to guarantee ideal mask quality. However, because of the high number of hot spots to repair in the design, that solution might be much time consuming in term of OPC and mask processing.

In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.

With continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 2, 5] show that even though the intrafield component stays the same, it becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. In a previous paper, the feasibility of anticipating the scanner levelling measurements (Level Sensor, Agile and Topography) has been shown [1]. This model, built using a multiple variable analysis (PLS: Partial Least Square regression) and GDS densities at different layers showed prediction capabilities of the scanner topography readings up to 0.78 Q² (the equivalent of R² for expected prediction). Using this model, care areas can be defined as parts of the field that cannot be seen nor corrected by the scanner, which can lead to local DOF shrinkage and printing issues. This paper will investigate the link between the care areas and the intrafield focus that can be seen at the wafer level, using offline topography measurements as a reference. Some improvements made on the model are also presented.

This paper presents the predicted imaging performance for an anamorphic EUV high NA (>0.5) exposure system with a 4x magnification in X orientation and a 8x magnification in Y orientation. It has a half field size with which the productivity requirements can be maintained. The main findings of the study are that horizontal and vertical features have very similar process window sizes despite magnification difference. A new definition of the Mask Error Factor (MEF) is introduced that is more relevant for anamorphic imaging; it shows that reticle CD errors have 2x larger impact for vertical compared to horizontal features. For dark field horizontal two-bar trenches relatively small mask induced focus shift was observed compared to the 0.33NA case, probably due to the relatively small Mask Angle of Incidence in the Y orientation with the 8x magnification. Finally a Ni type absorber has potential to further improve imaging performance.

EUV lithography (EUVL) for a limit resolution below 8 nm requires the numerical aperture (NA) of the projection optics to be larger than 0.50. For such a high-NA optics a configuration of 4x magnification, full field size of 26 x 33 mm² and 6’’ mask is not feasible anymore. The increased chief ray angle and higher NA at reticle lead to non-acceptable mask shadowing effects. These shadowing effects can only be controlled by increasing the magnification, hence reducing the system productivity or demanding larger mask sizes. We demonstrate that the best compromise in imaging, productivity and field split is a so-called anamorphic magnification and a half field of 26 x 16.5 mm² but utilizing existing 6’’ mask infrastructure. We discuss the optical solutions for such anamorphic high-NA EUVL.

In this work, the reverse replication of circular micro grating structures on glass substrates is implemented using an ultra-violet curable resin and a polydimethylsiloxane (PDMS) mold which has the same structure as the original circular grating master. Two different techniques (“double PDMS replication” and “polymer- PDMS replication”) are employed to fabricate those reversed circular micro grating structures. Surface profiling measurements show that in case of the polymer-PDMS replication the dimensions of the resulting circular grating structures closely approximate those of the master, while the grating height is slightly decreased in case of the double PDMS replication technique, mainly due to the use of the releasing agent. For both methods, the grating slopes of the circular gratings are almost unchanged, leading to the desired optical performance. The two techniques are quite useful for more accurate reverse replications of micro optical and photonic structures.

EUV Lithography now reaches the fab floor. The technology ramp up and integration with existing processes will require evolutionary steps in many aspects of the technology. For instance will it be necessary to reduce 3D mask effects like shadowing e.g. by introducing a thinner absorber structure. Continuous progress will be based on using new materials, adapted multilayers, and new reticle designs. Many of these developments are based on simulations and computer models for the design of the required structures and thus require data on the optical properties of the materials involved. In particular when addressing the reticle where the optical function is the target value. Using its more than 25 years of expertise in EUV metrology1, PTB operates instrumentation for reflectometry and scatterometry2 in the EUV and adjacent wavelength ranges and can provide the data for the determination of optical material parameters for individual thin layers. The need for sound optical parameter characterization for the development of alternative EUV materials was thoroughly motivated during the 2015 SPIE Advanced Lithography conference3. The data required is not readily available from databases, as thin film properties - depending on their deposition method and interfaces - may deviate significantly from standard bulk data4. Therefore, better optical constants and a continuous availability of the associated measurement tools are vital for further progress in EUV reticle and optical system design. The ability to vary relevant parameters like wavelength, angle of incidence (AOI), the plane of incidence and polarization is a prerequisite to gather sufficient data to model optical constants. We give details on PTB's measurement capabilities and accessible parameter space for optical material parameter characterization and show some representative data and results.

There are significant advantages of using the ReticleSense™ Airborne Particle Sensor (APSR) in reticle environments to locate and troubleshoot airborne particles as compared to traditional surface scan reticle, in-situ or hand-held methods. Time, resource and cost savings are identified.