Fault Tolerance Techniques For Highly Parallel Signal Processing Architectures

Jacob A. Abraham

doi:10.1117/12.960498

28 July 1986 Fault Tolerance Techniques For Highly Parallel Signal Processing Architectures

Jacob A. Abraham

Proceedings Volume 0614, Highly Parallel Signal Processing and Architectures; (1986) https://doi.org/10.1117/12.960498
Event: O-E/LASE'86 Symposium, 1986, Los Angeles, CA, United States

Abstract

This overview paper describes techniques for fault tolerance which can be applied to highly parallel signal processing architec-tures. Classical techniques are outlined and shown applicable to memories and data communications. The recent approach of algorithm-based fault tolerance, which tailors the fault tolerance to the systolic algorithm and processor architecture, is shown to be a natural one for such systems. Various data encoding techniques and resulting fault-tolerant systems are described and critiqued.

Citation Download Citation

Jacob A. Abraham "Fault Tolerance Techniques For Highly Parallel Signal Processing Architectures", Proc. SPIE 0614, Highly Parallel Signal Processing and Architectures, (28 July 1986); https://doi.org/10.1117/12.960498

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