System Architecture For High Speed Sorting Of Potatoes

J. A. Marchant; C. M. Onyango; M. J. Street

doi:10.1117/12.948993

21 March 1989 System Architecture For High Speed Sorting Of Potatoes

J. A. Marchant, C. M. Onyango, M. J. Street

Proceedings Volume 1004, Automated Inspection and High-Speed Vision Architectures II; (1989) https://doi.org/10.1117/12.948993
Event: 1988 Cambridge Symposium on Advances in Intelligent Robotics Systems, 1988, Boston, MA, United States

Abstract

This paper illustrates an industrial application of vision processing in which potatoes are sorted according to their size and shape at speeds of up to 40 objects per second. The result is a multi-processing approach built around the VME bus. A hardware unit has been designed and constructed to encode the boundary of the potatoes, to reducing the amount of data to be processed. A master 68000 processor is used to control this unit and to handle data transfers along the bus. Boundary data is passed to one of three 68010 slave processors each responsible for a line of potatoes across a conveyor belt. The slave processors calculate attributes such as shape, size and estimated weight of each potato and the master processor uses this data to operate the sorting mechanism. The system has been interfaced with a commercial grading machine and performance trials are now in progress.

Citation Download Citation

J. A. Marchant, C. M. Onyango, and M. J. Street "System Architecture For High Speed Sorting Of Potatoes", Proc. SPIE 1004, Automated Inspection and High-Speed Vision Architectures II, (21 March 1989); https://doi.org/10.1117/12.948993

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