Novel methodology to optimize wafer alignment to enhance 14nm on product overlay

Pavan Samudrala; Woong Jae Chung; Lokesh Subramany; Haiyong Gao; Nyan Aung; Seung Chul Oh; Shawn Lee; Erik Delvigne; Blandine Minghetti

doi:10.1117/12.2258137

24 March 2017 Novel methodology to optimize wafer alignment to enhance 14nm on product overlay

Pavan Samudrala, Woong Jae Chung, Lokesh Subramany, Haiyong Gao, Nyan Aung, Seung Chul Oh, Shawn Lee, Erik Delvigne, Blandine Minghetti

Author Affiliations +

Proceedings Volume 10147, Optical Microlithography XXX; 101471U (2017) https://doi.org/10.1117/12.2258137
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

With continuous shrink in feature dimensions, overlay tolerance for fabrication of transistors is getting more stringent. Achieving good overlay is extremely critical in getting good yield in HVM environment. It is widely understood that good alignment during exposure is critical for better on product overlay [1]. Conventional methods to choose alignment marks on ASML scanners are based on comparing alignment key performance indicators (KPIs) including signal quality, grid repeatability, etc. It is possible that even with good alignment KPIs, OPO is still impacted. In this paper, we propose aspects that need to be monitored to choose proper alignment marks. LIS (Litho In-Sight) alignment, Ideal overlay/APC parameter signatures are used to determine and validate wafer alignment. LIS alignment ‘Target and Profile selection’ analysis enables us to determine best alignment strategy between multiple strategies/marks based on overlay measurements. Analysis includes examining wafer to wafer OPO variation which is key indicator for alignment robustness. Varying overlay parameters within lot would indicate either large process instability or alignment mark signal instability. It is possible that alignment marks depending on their segmentation can be very differently impacted with the process. Ideal overlay/APC signature stability indicates healthy process and wafer alignment. Having similar APC signatures at corresponding layers would mean that there is no major process or alignment issue.

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Pavan Samudrala, Woong Jae Chung, Lokesh Subramany, Haiyong Gao, Nyan Aung, Seung Chul Oh, Shawn Lee, Erik Delvigne, and Blandine Minghetti "Novel methodology to optimize wafer alignment to enhance 14nm on product overlay", Proc. SPIE 10147, Optical Microlithography XXX, 101471U (24 March 2017); https://doi.org/10.1117/12.2258137

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KEYWORDS

Optical alignment

Overlay metrology

Lithium

Scanners

Data modeling

Roads

Yield improvement

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