Presentation + Paper
23 March 2020 Improvement of SADP CD control in 7nm BEOL application
Qi Lin, Toshiyuki Hisamura, Nui Chong, Jonathan Chang
Author Affiliations +
Abstract
Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.
Conference Presentation
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Qi Lin, Toshiyuki Hisamura, Nui Chong, and Jonathan Chang "Improvement of SADP CD control in 7nm BEOL application", Proc. SPIE 11327, Optical Microlithography XXXIII, 113270X (23 March 2020); https://doi.org/10.1117/12.2552168
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KEYWORDS
Metals

Critical dimension metrology

Semiconducting wafers

Silicon

Resistance

Etching

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