HDecoder: a hardware LDPC decoder using high level synthesis for phase modulated collinear holographic storage

Yifan Zhang; Qiang Cao; Lei Sun; Jie Yao; Changsheng Xie

doi:10.1117/12.2584981

4 December 2020 HDecoder: a hardware LDPC decoder using high level synthesis for phase modulated collinear holographic storage

Yifan Zhang, Qiang Cao, Lei Sun, Jie Yao, Changsheng Xie

Author Affiliations +

Proceedings Volume 11617, International Conference on Optoelectronic and Microelectronic Technology and Application; 1161713 (2020) https://doi.org/10.1117/12.2584981
Event: International Conference on Optoelectronic and Microelectronic Technology and Application, 2020, Nanjing, China

Abstract

Phase-modulated collinear holographic storage is promising high storage density at cost of high raw bit error rate. We first performed a simulation to analyze the bit-error-rate characteristics of phase-modulated collinear holographic storage under different noise intensity. To ensure high storage capacity with acceptable user biterror-rate, LDPC (Low Density Parity Check Code) is introduced to ensure data reliability. We further analyze the LDPC code error correction performance under different factors and determine the appropriate hardware parameters for the LDPC decoder. Finally, we use High Level Synthesis to fast implement and optimize an LDPC FPGA-based hardware decoder, named as HDecoder. HDecoder achieves 204Mbps decoding throughput, 150x and 4850x higher than CPU-based software decoder and the HLS-based vanilla hardware decoder. Compare to HLS-based vanilla LDPC decoder, HDecoder consumes 55x lower hardware resource per Mbps.

Citation Download Citation

Yifan Zhang, Qiang Cao, Lei Sun, Jie Yao, and Changsheng Xie "HDecoder: a hardware LDPC decoder using high level synthesis for phase modulated collinear holographic storage", Proc. SPIE 11617, International Conference on Optoelectronic and Microelectronic Technology and Application, 1161713 (4 December 2020); https://doi.org/10.1117/12.2584981

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