Parallel computation of CRC-code on an FPGA

Dat Tran; Nicolas Gorius; Shahid Aslam; George Nehmetallah

doi:10.1117/12.2586144

12 April 2021 Parallel computation of CRC-code on an FPGA

Dat Tran, Nicolas Gorius, Shahid Aslam, George Nehmetallah

Proceedings Volume 11755, Sensors and Systems for Space Applications XIV; 117550V (2021) https://doi.org/10.1117/12.2586144
Event: SPIE Defense + Commercial Sensing, 2021, Online Only

Conference Poster

Abstract

With the rapid advancement of imaging technology, space-based remote sensing instruments are becoming more sophisticated and are producing substantially more amounts of data for downloading. Data alteration is very likely to occur during the transmission over the long distances from probes to carrier spacecraft and subsequently back to Earth,. Cyclic Redundancy Check (CRC) is the most well-known data package error check technique which has been used in many applications. Unfortunately, due to its serial computation process, it could be a bottleneck for critical applications that require rapid processing. To overcome such issue, we present here a parallel CRC computational method based on an FPGA with simulation and testing to validate the methodology.

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Citation Download Citation

Dat Tran, Nicolas Gorius, Shahid Aslam, and George Nehmetallah "Parallel computation of CRC-code on an FPGA", Proc. SPIE 11755, Sensors and Systems for Space Applications XIV, 117550V (12 April 2021); https://doi.org/10.1117/12.2586144

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KEYWORDS

Error control coding

Field programmable gate arrays

Telecommunications

Algorithms

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