Semiconductor manufacturers are increasingly motivated to reduce overlay (OVL) target size. The scribe line area is in high demand, especially as width reduction efforts persist. Furthermore, since overlay control challenges require a higher sampling density, there is a growing need to place ultra-small targets inside the active chip, especially for devices with a large area. One of the main challenges of this new reality is producing smaller cell (grating) sizes to form smaller overlay targets, while maintaining compatible measurements to the standard target size of the same design. To overcome this challenge on typical scatterometry-based overlay (SCOL®) targets, we describe a method developed to perform the preliminary evaluation on a standard cell size of 8μm. This method selects a scalable setup by predicting performance on a 3-5um cell with the same target design (TD) parameters. This allows chipmakers to qualify the OVL measurement during process development on standard size targets, with the confidence that the optimized measurement conditions will be carried over to the smaller targets, saving time and real estate. However, even for scalable designs, target size reduction necessarily forces some size-performance tradeoffs: factors that are negligible for a standard target size can have significant impact on a scaled-down version of the same target design. In this paper we analyze these factors, show how they relate to measurement indicators, and present a method to apply such indicators toward setup selection. For each setup candidate this method can provide predicted performance and measurability as a function of cell size, a powerful tool for target area reduction.
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