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23 May 2022 Design of a 14 bit pipelined ADC
QingQing Liu, Gong Chen, Jia He, QingLin Zeng, Peng Xie
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Proceedings Volume 12254, International Conference on Electronic Information Technology (EIT 2022); 1225404 (2022) https://doi.org/10.1117/12.2639211
Event: International Conference on Electronic Information Technology (EIT 2022), 2022, Chengdu, China
Abstract
Based on 45nm process, a 14 bit 20 MS/s pipelined analog-to-digital converter (ADC) was designed. In this paper, the ring amplifier is used to replace the traditional operational amplifier (OTA). The ring amplifier has the advantage s of large bandwidth and good linearity, and the minimum power supply voltage of the ring amplifier is low, so the core power supply of the analog module and digital module of ADC is 1.2V, which reduces the overall power consumption of ADC. The ADC consisted of 7 stages, in which 2.5-bit/stage was applied from 1st to 6th stage and the last stage was a 2-bit Flash ADC. The ADC is tested with a sampling frequency of 250MS/s. The simulation results indicate that when the input signal frequency is 10.5 MHz, the SFDR of the ADC is 78.7dB and the ENOB is 11.36 bit; when the input signal frequency is 89.5 MHz, the SFDR can still reach 73dB and the ENOB can reach 11.2 bit.
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QingQing Liu, Gong Chen, Jia He, QingLin Zeng, and Peng Xie "Design of a 14 bit pipelined ADC", Proc. SPIE 12254, International Conference on Electronic Information Technology (EIT 2022), 1225404 (23 May 2022); https://doi.org/10.1117/12.2639211
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KEYWORDS
Amplifiers
Analog electronics
Digital signal processing
Quantization
Transistors
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