Paper
23 May 2022 Universal accelerator software and hardware collaborative design for YOLO algorithm
Minghao Wang, Xuesong Xie, Xiaoling Zhang, Liang Zhang
Author Affiliations +
Proceedings Volume 12254, International Conference on Electronic Information Technology (EIT 2022); 122542C (2022) https://doi.org/10.1117/12.2638600
Event: International Conference on Electronic Information Technology (EIT 2022), 2022, Chengdu, China
Abstract
YOLO (You Only Look Once) of target detection algorithms have complex model structure and large computation. However, in practical application scenarios, they not only need to meet the task requirements of low latency and low power consumption, but also face problems such as difficult deployment and long development cycle of YOLO algorithms. Based on the flexibility of embedded CPU software design and the advantages of Field Programmable Gate Array (FPGA) parallel computing, combined with the structural characteristics of YOLO algorithm, a universal hardware accelerator software/hardware co-design method for rapid deployment of YOLO algorithm is proposed to solve the above problems. In the hardware acceleration design, multi-channel parallel internal and external storage interaction, model parameter reordering, fixed-point, multi-dimensional parallelism tiling and other acceleration optimization techniques are adopted. In the software driver design, multiple versions of YOLO algorithm are compatible to achieve rapid deployment. Zynq7000 is used as the hardware platform to implement a YOLO algorithm universal hardware accelerator system with low delay and low power consumption. The results show that the energy efficiency ratio of this system can be improved by 132x compared with PC CPU and 120x compared with embedded CPU while implementing YOLOv4-tiny algorithm.
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Minghao Wang, Xuesong Xie, Xiaoling Zhang, and Liang Zhang "Universal accelerator software and hardware collaborative design for YOLO algorithm", Proc. SPIE 12254, International Conference on Electronic Information Technology (EIT 2022), 122542C (23 May 2022); https://doi.org/10.1117/12.2638600
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KEYWORDS
Convolution

Detection and tracking algorithms

Field programmable gate arrays

Data modeling

Digital signal processing

Algorithm development

Data storage

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