Presentation + Paper
28 April 2023 Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning
Author Affiliations +
Abstract
Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (DTCO) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the study, mask materials are compared. Indeed, in EUV domain there is interest to use alternative mask absorbers like Ruthenium alloys as an alternative to Tantalum-based absorbers [4,5,6].
Conference Presentation
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ana-Maria Armeanu, Evgeny Malankin, Neal Lafferty, Chih-I Wei, Monica Kempsell Sears, Germain Fenger, Xima Zhang, Werner Gillijns, Darko Trivkovic, Ryoung-han Kim, and Jeonghoon Lee "Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning", Proc. SPIE 12495, DTCO and Computational Patterning II, 124950A (28 April 2023); https://doi.org/10.1117/12.2660413
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KEYWORDS
Photomasks

Extreme ultraviolet

Source mask optimization

Lithography

Optical proximity correction

Resolution enhancement technologies

Optical lithography

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