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As the technology node scales down below nanometer, the design rules significantly increase, which in turn results in the huge search problems of the chip design with an early-stage technology. DTCO (Design-Technology Co-Optimization) becomes a key methodology in semiconductor industry to overcome the limitation of physical scaling and transistor density, and to improve performance and power efficiency [1-2]. However, DTCO induces huge increase of design spaces in physical implementation since chip designers should tune the technology related variables along with the conventional design variables at the early technology stage. ML (machine learning) is a powerful technique when tuning and optimizing such complicated parameters in technology and design [3]. Synopsys DSO.ai (Design Space Optimization AI) is an early innovator of ML (Machine Learning) in EDA (Electronic Design Automation) area, where the tool uses advancements of RL (Reinforcement Learning) to effectively search the massive design space for global near-optimal targets [4]. In this paper, we report DSO.ai applications on 3nm technology and designs, such as PPA (Performance-Power-Area) improvements in both HP (high performance) and HD (high density) libraries, NDR (non-default rule) routing on both clock and signal nets, LP (layer promotion), density control, routing wire and via cost tuning, and more. Furthermore, we utilize ML capability in searching and optimizing technology parameters, e.g., key design pitches and design rules, as well as design parameters, e.g., via/wire cost, placeholder densities, legalization and routing strategies, and other EDA settings, to maximize PPA metric and to minimize DRC violation. Our goal is to find the best values of the initial parameters from an early technology and design stages and to encapsulate them in RM (Reference Methodology) script to provide the designer with the mega switch in entire design flows. Parameter range (to be explored) and evaluation metrics (to score QOR) are defined, then DSO.ai explores search spaces and trains itself to minimize the optimization cost. Optimized parameter values are evaluated against the reference parameters to reproduce the benefit across various designs and technology collaterals. In this manner, different parameters can be optimized given design methodology. This iterative process can be extended to optimize all design technology parameters to maximize PPA on 3nm design technology and designs and beyond. Proposed approach applied to optimize achievable core area and improve max frequency, respectively. Design flow with ML-assisted parameter could reproduce improvement across the different size and different styles of the benchmark designs. Optimization for achievable core area could reduce -0.5% at cell-driven design and -0.6% at route-driven design. Optimization for performance could improve the frequency of +1.42% at cell-driven design and +1.43% at route-driven design in Samsung 3nm technology.
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