A 16-bit high-low two-stage digital-to-analog converter

Bo Qiao; Xiaolong Li

doi:10.1117/12.2685522

28 July 2023 A 16-bit high-low two-stage digital-to-analog converter

Bo Qiao, Xiaolong Li

Proceedings Volume 12716, Third International Conference on Digital Signal and Computer Communications (DSCC 2023); 127161D (2023) https://doi.org/10.1117/12.2685522
Event: Third International Conference on Digital Signal and Computer Communications (DSCC 2023), 2023, Xi'an, China

Abstract

Taking the typical DAC binary code structure "R-2R" type DAC structure as an example, as the number of bits increases, the resistance structure also increases, resulting in excessive layout and power consumption. In addition, the analog switches in the R-2R resistor network are out of sync and cause voltage spikes in the output signal, which affects the accuracy of the digital-to-analog converter. In order to improve the accuracy of digital-to-analog converters, reduce chip area and reduce power consumption, a 16-bit high-low two-stage DAC is designed based on the "R-2R" DAC using 0.18- μm CMOS technology, which is a high-bit thermometer code network structure and a low-bit binary code network structure, respectively, and uses a Class AB amplifier to amplify the signal. Spectre simulations show that the DAC consumes 180uA of current when the supply voltage and reference voltage are 3.3V, and can drive a capacitive load of 10pF.

Citation Download Citation

Bo Qiao and Xiaolong Li "A 16-bit high-low two-stage digital-to-analog converter", Proc. SPIE 12716, Third International Conference on Digital Signal and Computer Communications (DSCC 2023), 127161D (28 July 2023); https://doi.org/10.1117/12.2685522

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