KIM200: a tagged-RISC architecture for gallium arsenide implementation

Jean-Claude Heudin; Christophe Metivier

doi:10.1117/12.21138

1 January 1990 KIM200: a tagged-RISC architecture for gallium arsenide implementation

Jean-Claude Heudin, Christophe Metivier

Proceedings Volume 1293, Applications of Artificial Intelligence VIII; (1990) https://doi.org/10.1117/12.21138
Event: 1990 Technical Symposium on Optics, Electro-Optics, and Sensors, 1990, Orlando, FL, United States

Abstract

This paper describes a new RISC architecture being designed to take advantage of GaAs technology for high performance symbolic processing. First, we present our top-down methodology which starts from the study of applications requirements, technology constraints, and concludes with the choice of the most suitable architecture. Then, next paragraphs describe carefully the architecture and its originalities. It can be summerized as a tagged-RISC embedded processor, which is able to operate with a 200 Mhz clock rate. As a conclusion, we give performance goals and simulation results.

Citation Download Citation

Jean-Claude Heudin and Christophe Metivier "KIM200: a tagged-RISC architecture for gallium arsenide implementation", Proc. SPIE 1293, Applications of Artificial Intelligence VIII, (1 January 1990); https://doi.org/10.1117/12.21138

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