As semiconductor device structures continue to shrink and increase its complexity, the need for precise measurement techniques extends beyond single-layer patterning to encompass overlay and Edge Placement Error (EPE) across multiple layers. Traditionally, overlay and EPE have been managed using dedicated patterns and equipment, respectively. However, as manufacturing processes become more intricate, there arises a necessity to measure these parameters directly on actual device patterns. Addressing this demand, High Voltage-Scanning Electron Microscopy (HV-SEM) emerges as a viable tool for on-device-overlay measurement. Nevertheless, challenges persist in achieving accurate measurements using seethrough Backscattered Electron (BSE) imaging due to low contrast and sharpness resulting from electron diffusion through upper-layer patterns. This impedes precise contour extraction and reduces pattern measurement sensitivity. Moreover, in layouts where pattern contours between layers are closely spaced, precise contour extraction becomes even more challenging. To address these issues, a specialized contour extraction function is essential for achieving precise and stable pattern extraction from BSE images. In this paper, we propose a novel HV-SEM overlay measurement methodology utilizing active contour model with Electron Beam (EB) simulation. Synthetic images, designed to emulate the latest device structures and based on BSE features obtained through EB simulation, were employed for evaluation. The results demonstrate the method's robustness to noise and its ability to accurately extract the contours of partially hidden lowerlayer patterns. The proposed approach will enhance the accuracy of HV-SEM overlay measurements, thereby expanding the utility of HV-SEM see-through BSE imaging in semiconductor manufacturing processes.
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