A 0.9V 11.74-13.68GHz class-F2,3 CMOS VCO with typical phase noise of -123.66dBc/Hz@1MHz

Jishu Sun; Xiaodong Liu; Zhizhe Liu; Cong Li; Di Sun; Xin Yin; Hongjie Yin

doi:10.1117/12.3025853

1 April 2024 A 0.9V 11.74-13.68GHz class-F_2,3 CMOS VCO with typical phase noise of -123.66dBc/Hz@1MHz

Jishu Sun, Xiaodong Liu, Zhizhe Liu, Cong Li, Di Sun, Xin Yin, Hongjie Yin

Proceedings Volume 13081, Third International Conference on Advanced Manufacturing Technology and Electronic Information (AMTEI 2023); 130810N (2024) https://doi.org/10.1117/12.3025853
Event: 2023 3rd International Conference on Advanced Manufacturing Technology and Electronic Information (AMTEI 2023), 2023, Tianjin, China

Abstract

To enhance the overall performance of the phase-locked loop frequency synthesizer, this paper presents a low-phase noise dual-core voltage-controlled oscillator (VCO) designed with a Class-F_2,3 architecture. Utilizing the 55-nm CMOS, the wide tuning range is achieved through variable capacitance and switch capacitor arrays. The use of adjacent-layer coupled transformer structures, with the adjustment of capacitance ratios in two resonant cavities, facilitates low phase noise. Postsimulation results indicate that the frequency tuning range of the VCO is 11.74-13.68 GHz. The VCO achieves phase noise of -123.66 dBc/Hz@1MHz at 11.74 GHz with figure of merit (FoM) of 185.7dBc/Hz and FoMT of 189.9dBc/Hz. The oscillator core consumes 67mW at 0.9V supply.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Jishu Sun, Xiaodong Liu, Zhizhe Liu, Cong Li, Di Sun, Xin Yin, and Hongjie Yin "A 0.9V 11.74-13.68GHz class-F_2,3 CMOS VCO with typical phase noise of -123.66dBc/Hz@1MHz", Proc. SPIE 13081, Third International Conference on Advanced Manufacturing Technology and Electronic Information (AMTEI 2023), 130810N (1 April 2024); https://doi.org/10.1117/12.3025853

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