Paper
1 July 1991 Automated approach to the correlation of defect locations to electrical test results to determine yield reducing defects
M. Michael Slama, Angela C. Patterson
Author Affiliations +
Abstract
Automated defect detection using various techniques (including holography, digital image processing and particle detection) has provided process engineers with defect distributions and densities for all process levels. However, defect detection systems alone cannot differentiate between killer and nuisance defects, and can only give an indication of the potential yield reducing problems. The location of the defect with respect to the process level is important in determining the impact on the final device. Recent techniques have been developed to automatically separate killer defects from nuisance defects. This paper show how this technique is used to isolate the yield reducing defects. The method used shows how results from electrical test can be correlated with defect inspection results.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
M. Michael Slama and Angela C. Patterson "Automated approach to the correlation of defect locations to electrical test results to determine yield reducing defects", Proc. SPIE 1464, Integrated Circuit Metrology, Inspection, and Process Control V, (1 July 1991); https://doi.org/10.1117/12.44471
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KEYWORDS
Inspection

Semiconducting wafers

Raster graphics

Feedback loops

Image processing

Digital image processing

Failure analysis

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