VLSI implementation of a buffer, universal quantizer, and frame-rate-control processor

H. Uwabu; Eiji Kakii; R. Lacombe; Masanori Maruyama; Hiroshi Fujiwara

doi:10.1117/12.50298

1 November 1991 VLSI implementation of a buffer, universal quantizer, and frame-rate-control processor

H. Uwabu, Eiji Kakii, R. Lacombe, Masanori Maruyama, Hiroshi Fujiwara

Proceedings Volume 1605, Visual Communications and Image Processing '91: Visual Communication; (1991) https://doi.org/10.1117/12.50298
Event: Visual Communications, '91, 1991, Boston, MA, United States

Abstract

The CCITT Recommendation H.261 [1] describes the video coding and decoding method for the moving picture component of audiovisual services at the rates of px64 kbit/s, where p is in the range 1 to 30. Accordingly, several chip sets realizing these methods have been announced[3,4,5,6]. In this paper, a new architecture and implementation of an adaptive coding controller chip is reported. The main features of the chip include: (A) Adaptive Weighted Image Quality Control Capability, (B) High Speed Operation and (C) External Control Capability for Coding Control. The chip is implemented with CMOS standard cells and contains approximately 38,000 gates.

Citation Download Citation

H. Uwabu, Eiji Kakii, R. Lacombe, Masanori Maruyama, and Hiroshi Fujiwara "VLSI implementation of a buffer, universal quantizer, and frame-rate-control processor", Proc. SPIE 1605, Visual Communications and Image Processing '91: Visual Communication, (1 November 1991); https://doi.org/10.1117/12.50298

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