Minimization of false defect reporting in a patterned silicon wafer inspection system

John R. Dralla; John C. Hoff

doi:10.1117/12.130297

1 August 1992 Minimization of false defect reporting in a patterned silicon wafer inspection system

John R. Dralla, John C. Hoff

Proceedings Volume 1661, Machine Vision Applications in Character Recognition and Industrial Inspection; (1992) https://doi.org/10.1117/12.130297
Event: SPIE/IS&T 1992 Symposium on Electronic Imaging: Science and Technology, 1992, San Jose, CA, United States

Abstract

The detection of defects in sub-micron semiconductor devices has reached new limits in recent years. Detection sensitivity limits are now at 0.25 microns and are being driven to 0.1 microns for 256M DRAM production. At these levels of defect detection sensitivity the need for discrimination between true defects and false defects becomes extremely important. Users of such systems cannot afford to manually sort through the large numbers of total reported defects, true and false, and thereby isolate which defects will cause yield loss. This paper discusses a system that has been developed for semiconductor in-process wafer inspection which incorporates a proprietary `statistical image'' technique and other user adjustable system parameters to minimize the frequency of false positives. The results of this study indicate that this is particularly important for the later stages of device manufacture where the thin films contain random texture which results in the potential for many false positives.

Citation Download Citation

John R. Dralla and John C. Hoff "Minimization of false defect reporting in a patterned silicon wafer inspection system", Proc. SPIE 1661, Machine Vision Applications in Character Recognition and Industrial Inspection, (1 August 1992); https://doi.org/10.1117/12.130297

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