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Variations in wafer substrate film stacks can have a significant effect upon the resist critical dimension (CD) and exposure level for layers patterned to fabricate advanced four level metal BIMOS devices. In the fabrication of these VLSI devices, patterning is frequently performed on film stacks of varying thickness and optical properties. PROLITH was used to simulate lithography behavior on actual device film stacks, and the results compared favorably to data collected from actual product wafers. Simulations can be used to accurately predict the exposure changes needed to compensate for changes in film thickness and film stack upon CD. Good agreement was obtained for most cases studied, with less than 3% deviation between the experimental and simulated results being typical. In most cases, the PROLITH simulated data and empirically determined results were in good agreement. Thin film reflectivity is also observed to have a strong influence on CD variation. In via patterning experiments, for example, vias printed with only resist exhibited “reflective notching dominated” CD 3-sigma variation of 0.10 pm greater than that observed where an optimized ARC process was employed under the resist to minimize substrate reflectivity. The significant improvements in CD variation have been generally correlated with reductions and/or optimizations in substrate reflectivity. Electrical probe CD data for backend metal layers has also been evaluated for thin film notching behavior, and as seen for via layer notching, the CD variation is minimized by applying the results from PROLITH reflectivity analysis. The significant improvements in CD variation have been correlated with the reduction and optimization of substrate reflectivity, which is determined by the combination(s) of dielectric and resist contributors.
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