Performance consideration for the scaling of submicron on-chip interconnections

Yuh-J. Mii

doi:10.1117/12.145476

21 May 1993 Performance consideration for the scaling of submicron on-chip interconnections

Yuh-J. Mii

Proceedings Volume 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations; (1993) https://doi.org/10.1117/12.145476
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States

Abstract

Effects of long wire RC delay to circuit and system performance are investigated for sub- micron on-chip interconnections corresponding to 0.75 to 0.25 micrometers CMOS technologies. A system performance model based on hypothetic microprocessors, projected from previous generations, is introduced for the performance analysis. From the analysis, it is found that non-scaled upper wiring levels (wide wires) for long global interconnections is the most effective approach to improve system performance with sub-micron-pitch interconnections. It can provide 70% performance improvement over the wide wire approach, which increase only wire width for long interconnections. The fat wire approach, however, requires some technology modifications, as well as one more wiring level than conventional approaches.

Citation Download Citation

Yuh-J. Mii "Performance consideration for the scaling of submicron on-chip interconnections", Proc. SPIE 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations, (21 May 1993); https://doi.org/10.1117/12.145476

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