Hierarchical multiprocessor system for video signal processing

Joerg Wilberg; Matthias Schoebinger; Peter Pirsch

doi:10.1117/12.131378

1 November 1992 Hierarchical multiprocessor system for video signal processing

Joerg Wilberg, Matthias Schoebinger, Peter Pirsch

Proceedings Volume 1818, Visual Communications and Image Processing '92; (1992) https://doi.org/10.1117/12.131378
Event: Applications in Optical Science and Engineering, 1992, Boston, MA, United States

Abstract

The architecture of a hierarchical multiprocessor (MP) system for videocoding is discussed. The topmost level of the proposed MP-system consists of identical, bus connected processing elements (PEs). A heterogeneous MIMD (multiple instruction multiple data) architecture is proposed for the PE. The PE contains a shared local memory and processing units, which are adapted to specific tasks. A strategy for optimizing the efficiency (defined by inverse area X processing time) at different levels of the hierarchy is proposed. This allows to realize an H.261 videocodec with only a few, if not a single PE. The efficiency of each PE can be increased, if multiple datablocks are processed concurrently within the PE (macropipelining). On the basis of a 1.0 micrometers CMOS technology a single PE (clock rate 50 MHz) can process the H.261 videocodec (except variable length coding and decoding) for CIF images at a frame rate of 18 Hz. Assuming an 0.6 micrometers CMOS technology, a single PE is expected to process frame rates of 30 Hz. A rough estimate of the silicon area for this technology is in the order of 100 mm².

Citation Download Citation

Joerg Wilberg, Matthias Schoebinger, and Peter Pirsch "Hierarchical multiprocessor system for video signal processing", Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); https://doi.org/10.1117/12.131378

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