CMOS processor element for a fault-tolerant SVD array

Kishore Kota; Joseph R. Cavallaro

doi:10.1117/12.160459

1 November 1993 CMOS processor element for a fault-tolerant SVD array

Kishore Kota, Joseph R. Cavallaro

Proceedings Volume 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV; (1993) https://doi.org/10.1117/12.160459
Event: SPIE's 1993 International Symposium on Optics, Imaging, and Instrumentation, 1993, San Diego, CA, United States

Abstract

This paper describes the VLSI implementation of a CORDIC based processor element for use in a fault-reconfigurable systolic array to compute the singular value decomposition (SVD) of a matrix. The chip implements a time redundant fault tolerance scheme, which allows processors adjacent to a faulty processor to act as computation backup during the systolic idle time. Also, processors around a fault collaborate to reroute data around the faulty processor. This form of time redundancy is attractive when tolerance to a few faults needs to be achieved with little hardware overhead.

Citation Download Citation

Kishore Kota and Joseph R. Cavallaro "CMOS processor element for a fault-tolerant SVD array", Proc. SPIE 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV, (1 November 1993); https://doi.org/10.1117/12.160459

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