Process optimization for 0.35-um i-line lithography

Cesar M. Garza Sr.; William L. Krisa; Anthony Yen; Jing S. Shu

doi:10.1117/12.175458

17 May 1994 Process optimization for 0.35-um i-line lithography

Cesar M. Garza Sr., William L. Krisa, Anthony Yen, Jing S. Shu

Proceedings Volume 2197, Optical/Laser Microlithography VII; (1994) https://doi.org/10.1117/12.175458
Event: SPIE's 1994 Symposium on Microlithography, 1994, San Jose, CA, United States

Abstract

Extending i-line lithography to 0.35 micrometers processing is a realistic possibility because of improvements in photoresists, steppers, track equipment, and reticle technology. The manufacturing of 0.35 micrometers devices can include as many as twenty lithography levels, however, most of the critical issues can be addressed in printing the gate and contact levels. The optimized process for 0.35$ mum gates and contacts is presented in this paper. Even with advanced photoresists, enhancement techniques were needed to meet the processing requirements for these two levels on actual topography. The enhancement techniques used for the gate level were a TARC and modified illumination. A TARC was required to improve linewidth uniformity, and modified illumination to improve focus budget and exposure latitude. For contacts, attenuated phase shift was required to achieve workable focus latitude. The data presented shows that an optimized i-line resist processes with enhancement techniques can meet the requirements of volume production of 0.35 micrometers devices.

Citation Download Citation

Cesar M. Garza Sr., William L. Krisa, Anthony Yen, and Jing S. Shu "Process optimization for 0.35-um i-line lithography", Proc. SPIE 2197, Optical/Laser Microlithography VII, (17 May 1994); https://doi.org/10.1117/12.175458

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KEYWORDS

Photoresist processing

Semiconducting wafers

Lithography

Reticles

Photoresist materials

Scanning electron microscopy

Manufacturing

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