Hierarchical multiprocessor-based image-analysis system

M. V. Raghunadh; M. V.G.V. Prasad Babu; J. P. Raina

doi:10.1117/12.205489

23 March 1995 Hierarchical multiprocessor-based image-analysis system

M. V. Raghunadh, M. V.G.V. Prasad Babu, J. P. Raina

Proceedings Volume 2421, Image and Video Processing III; (1995) https://doi.org/10.1117/12.205489
Event: IS&T/SPIE's Symposium on Electronic Imaging: Science and Technology, 1995, San Jose, CA, United States

Abstract

Hierarchial structures permit distributed computing and multitasking for processing the partitionable image data. A two level hierarchial multiprocessor employing the 68000 master processor, three 8085 slave processors, shared memory mapping, VME backplane bus and dedicated operating system is presented in this paper. The task generation, scheduling and interprocessor communication is under OS control. Image processing algorithms like edge detection, segmentation, smoothing and compression were performed by the master and slaves simultaneously.

Citation Download Citation

M. V. Raghunadh, M. V.G.V. Prasad Babu, and J. P. Raina "Hierarchical multiprocessor-based image-analysis system", Proc. SPIE 2421, Image and Video Processing III, (23 March 1995); https://doi.org/10.1117/12.205489

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