Reconfigurable computing for multimedia DSP applications

Erdogan Simsek; Abdul Wahab; Kishan Jainandunsing

doi:10.1117/12.221327

19 September 1995 Reconfigurable computing for multimedia DSP applications

Erdogan Simsek, Abdul Wahab, Kishan Jainandunsing

Proceedings Volume 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing; (1995) https://doi.org/10.1117/12.221327
Event: Photonics East '95, 1995, Philadelphia, PA, United States

Abstract

The application of reconfigurable computing to exploit the inherent serialism in DSP algorithms is investigated with the aim of building cost-effective, real-time hardware. The DSP algorithm is expected to be decomposed so that the most compute intensive and data flow oriented part is separated from the less compute intensive and more control flow oriented part. The different modules in the compute intensive part are expected to be serialized and implemented on a reconfigurable platform. The proposed architecture consists of an array of a minimum of two Field Programmable Gate Arrays (FPGAs). The FPGAa are grouped in two sets such that when one set executes the current batch of modules the second set could be configured to execute the next batch of modules. The control flow oriented part of the algorithm is implemented on a DSP processor.

Citation Download Citation

Erdogan Simsek, Abdul Wahab, and Kishan Jainandunsing "Reconfigurable computing for multimedia DSP applications", Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); https://doi.org/10.1117/12.221327

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