Paper
22 October 1996 Novel high-speed bit-parallel multiply accumulate arithmetic architecture
Vishwas M. Rao, Behrouz Nowrouzian
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Abstract
This paper presents an architecture for high-speed bit- parallel multiply-accumulate arithmetic operation. This architecture employs the modified-Booth recoding algorithm for multiplication, and a kernel using mixed (sign, value)- encoded signed-binary (SB) and two's complement (TC) computation for carry-free generation of the SB partial product sums. The final SB partial product sum undergoes full-precision accumulation, rounding, and overflow correction concurrently, to facilitate a high-speed overall operation. A high-performance architecture is proposed for IEEE Standard 754 default rounding of the SB result. This architecture exploits the carry-free property of redundant number addition to perform the rounding operation, again concurrently with the multiplication and accumulation operations. The conversion of the final rounded SB number into its corresponding TC format is achieved by using a fast pipelined lookahead converter. The resulting multiply- accumulate arithmetic architecture is subsequently parameterized for ASIC implementations using the Actel 1.2 (mu) FPGA technology parameters. It is demonstrated that the use of (sign, value)-encoding leads to combined area and time efficient implementations.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Vishwas M. Rao and Behrouz Nowrouzian "Novel high-speed bit-parallel multiply accumulate arithmetic architecture", Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); https://doi.org/10.1117/12.255442
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Cited by 2 scholarly publications.
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KEYWORDS
Computer architecture

Digital signal processing

Chromium

Standards development

Clocks

Logic

Computer simulations

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