Plasma-induced oxide contamination in a 0.35-um CMOS process

Martin P. Karnett; Jingrong Zhou; Sumanta Ghosh; Danny Echtle; L. Fritz; Martin Manley; Gregory S. Scott

doi:10.1117/12.250843

12 September 1996 Plasma-induced oxide contamination in a 0.35-um CMOS process

Martin P. Karnett, Jingrong Zhou, Sumanta Ghosh, Danny Echtle, L. Fritz, Martin Manley, Gregory S. Scott

Proceedings Volume 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II; (1996) https://doi.org/10.1117/12.250843
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

Plasma contamination in a 0.35 micrometer triple-level metal CMOS process was investigated in response to anomalous dc parametric test data. Electrical PMOS transistor performance and both physical and electrical gate oxide thickness were significantly degraded upon exposure of a sacrificial oxide to a plasma ash following a masked, P-channel threshold adjust ion implant. The contamination was isolated to a specific asher, found to be radial in nature across a wafer, and consistently worse in one of the two chambers used during the ash process. The contamination dramatically reduced the wet etch rate of the sacrificial oxide, leading to incomplete removal prior to gate oxide growth. Increasing the wet strip time of the sacrificial oxide improved the ability to remove this contaminated film, but was limited by minimal field oxide thickness requirements to avoid field inversion. Transferring the ash process to an alternative, low-damage, down-stream asher eliminated the plasma contamination.

Citation Download Citation

Martin P. Karnett, Jingrong Zhou, Sumanta Ghosh, Danny Echtle, L. Fritz, Martin Manley, and Gregory S. Scott "Plasma-induced oxide contamination in a 0.35-um CMOS process", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); https://doi.org/10.1117/12.250843

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