New architecture for MPEG-2 real-time encoding

Mansour Zuair; Dikran S. Meliksetian; C. Y. Roger Chen

doi:10.1117/12.263510

17 January 1997 New architecture for MPEG-2 real-time encoding

Mansour Zuair, Dikran S. Meliksetian, C. Y. Roger Chen

Proceedings Volume 3021, Multimedia Hardware Architectures 1997; (1997) https://doi.org/10.1117/12.263510
Event: Electronic Imaging '97, 1997, San Jose, CA, United States

Abstract

A new architecture for real-time MPEG-2 encoding/decoding is presented in this paper. This architecture is based on an array of TI MVPs. The main feature of this architecture is its programmability. The inherent parallelism of the MPEG-2 algorithm is investigated in order to map it to the processor array. An I/O algorithm for the major encoding function, motion estimation, is developed to demonstrate the possibility of overlapping processing and I/O.

Citation Download Citation

Mansour Zuair, Dikran S. Meliksetian, and C. Y. Roger Chen "New architecture for MPEG-2 real-time encoding", Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); https://doi.org/10.1117/12.263510

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