Stepper NA/PC optimization DOE for i-line masking

Chung Yih Lee; Wei Wen Ma; Alex Tsun-Lung Cheng; Kia Huat Gan

doi:10.1117/12.324359

3 September 1998 Stepper NA/PC optimization DOE for i-line masking

Chung Yih Lee, Wei Wen Ma, Alex Tsun-Lung Cheng, Kia Huat Gan

Author Affiliations +

Proceedings Volume 3507, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV; (1998) https://doi.org/10.1117/12.324359
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

In this paper we present a statistical experiment design for stepper NA/PC optimization. The design starts with 2-level 3-factor full factorial. After optimizing ring width, we further optimize NA/PC with a 3-level design. Two responses of DoF and EL are measured using CD-SEM. Process fluctuation is simulated by using wafers with slightly different resist thickness as replication runs. Special stepper jobfile is created top expose different NA/PC settings on the same wafer at adjacent fields in order to eliminate the bias caused by center-of-edge and wafer-to-wafer variation. Production verification of the DOE results is also reported.

Citation Download Citation

Chung Yih Lee, Wei Wen Ma, Alex Tsun-Lung Cheng, and Kia Huat Gan "Stepper NA/PC optimization DOE for i-line masking", Proc. SPIE 3507, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV, (3 September 1998); https://doi.org/10.1117/12.324359

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