Paper
8 October 1998 Dynamically programmable cache
Mouna Nakkar, John A. Harding, David A. Schwartz, Paul D. Franzon, Thomas Conte
Author Affiliations +
Proceedings Volume 3526, Configurable Computing: Technology and Applications; (1998) https://doi.org/10.1117/12.327035
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States
Abstract
Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mouna Nakkar, John A. Harding, David A. Schwartz, Paul D. Franzon, and Thomas Conte "Dynamically programmable cache", Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); https://doi.org/10.1117/12.327035
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Cited by 4 scholarly publications.
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KEYWORDS
Field programmable gate arrays

Convolution

Motion estimation

Switching

Data storage

Image filtering

Data processing

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