Paper
13 November 2000 Combined unsigned and two's complement saturating multipliers
Michael J. Schulte, Mustafa Gok, Pablo I. Balzola, Robert W. Brocato
Author Affiliations +
Abstract
In many digital signal processing and multimedia applications, results that overflow are saturated to the most positive or most negative representable number. This paper presents efficient techniques for performing saturating n-bit integer multiplication on unsigned and two's complement numbers. Unlike conventional techniques for saturating multiplication, which compute a 2n-bit product and then examine the n most significant product bits to determine if overflow has occurred, the techniques presented in this paper compute only the (n + 1) least significant bits of the product. Specialized overflow detection units, which operate in parallel with the multiplier, determine if overflow has occurred and the product should be saturated. These techniques are applied to designs for saturating array multipliers that perform either unsigned or two's complement saturating integer multiplication, based on an input control signal. Compared to array multipliers that use conventional methods for saturation, these multipliers have about half as much area and delay.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael J. Schulte, Mustafa Gok, Pablo I. Balzola, and Robert W. Brocato "Combined unsigned and two's complement saturating multipliers", Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); https://doi.org/10.1117/12.406496
Lens.org Logo
CITATIONS
Cited by 7 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Multiplexers

Polonium

Digital signal processing

Logic

Signal processing

Multimedia

Virtual colonoscopy

RELATED CONTENT

A plug in to Eclipse for VHDL source codes ...
Proceedings of SPIE (October 15 2012)
Flexible arithmetic and logic unit for multimedia processing
Proceedings of SPIE (December 24 2003)
Design alternatives for barrel shifters
Proceedings of SPIE (December 06 2002)
Packed arithmetic on a prefix adder (PAPA)
Proceedings of SPIE (December 06 2002)
CMOS/SOS Microsignal Processor
Proceedings of SPIE (December 08 1978)

Back to Top