Wafer-level surface-mountable chip size packaging for MEMS and ICs

Stephane Renard

doi:10.1117/12.395635

15 August 2000 Wafer-level surface-mountable chip size packaging for MEMS and ICs

Stephane Renard

Proceedings Volume 4176, Micromachined Devices and Components VI; (2000) https://doi.org/10.1117/12.395635
Event: Micromachining and Microfabrication, 2000, Santa Clara, CA, United States

Abstract

TRONIC'S Microsystems has developed in collaboration with LETI and ELA Recherche a Chip Size Packaging for MEMS and ICs using standard MST technologies and batch wafer processing. It allows to integrate on a single package the Electro-Mechanical Structure of the circuits, the connections and the encapsulation. After dicing, the device which is a package of its own can be easily handled and directly mounted on a circuit board. The connection pads allows the mounting on a board using standard Surface Mounting Technologies and the reworkability.

Citation Download Citation

Stephane Renard "Wafer-level surface-mountable chip size packaging for MEMS and ICs", Proc. SPIE 4176, Micromachined Devices and Components VI, (15 August 2000); https://doi.org/10.1117/12.395635

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