Compiler for a dynamically reconfigurable processor with cell-array structures

Fumihiro Hatano; Takayuki Morishita; Kiyotaka Komoku; Iwao Teramoto

doi:10.1117/12.402513

6 October 2000 Compiler for a dynamically reconfigurable processor with cell-array structures

Fumihiro Hatano, Takayuki Morishita, Kiyotaka Komoku, Iwao Teramoto

Proceedings Volume 4212, Reconfigurable Technology: FPGAs for Computing and Applications II; (2000) https://doi.org/10.1117/12.402513
Event: Information Technologies 2000, 2000, Boston, MA, United States

Abstract

An extensive study has been made of the reconfigurable Cell-Array processor that realizes very high-speed parallel computations. Our processor is featured by the architecture such that the configuration can be dynamically and optimally rearranged in real-time by changing the pipeline length or the registry-area depth in macro-Cell units of memories and accumulators. In this processor, therefore, a much smaller size of instruction codes and also a much shorter reconfiguration time are required than in the conventional FPGAs with small-scale logic layers. This paper described a newly developed compiler as the alternative to that using the circuit designs, which requires a long labor even with a well-trained skill. This compile application analyzes a program written with the C-language, using the C-Language is able to use a lot of programs of the past, and produces instruction codes containing information about hardware configurations. According to the structure of hardware used, the compiler can find out the optimal configuration, involving the most efficient depth of pipelined accumulations and parallel calculations. The details of the program analysis are shown with the utility of the compiler in the reconfigurable cell-array processor.

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Fumihiro Hatano, Takayuki Morishita, Kiyotaka Komoku, and Iwao Teramoto "Compiler for a dynamically reconfigurable processor with cell-array structures", Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); https://doi.org/10.1117/12.402513

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KEYWORDS

Parallel computing

Array processing

Computer architecture

Process modeling

Switches

Process control

Software development

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