High-performance reconfigurable constant coefficient multiplier implementations

Philip B. James-Roxby; Brandon J. Blodget

doi:10.1117/12.402519

6 October 2000 High-performance reconfigurable constant coefficient multiplier implementations

Philip B. James-Roxby, Brandon J. Blodget

Proceedings Volume 4212, Reconfigurable Technology: FPGAs for Computing and Applications II; (2000) https://doi.org/10.1117/12.402519
Event: Information Technologies 2000, 2000, Boston, MA, United States

Abstract

The use of dynamic reconfiguration appears extremely attractive for implementing adaptive processing algorithms. Often, the adaption involves updating look-up tables based on a parameter which can only be determined at run-time. For reasons of efficiency, these look-up tables are read-only to the rest of the circuitry. This paper compares the use of run-time reconfiguration and read-only look-up tables, with similar implementations using writable memories. The application under consideration is the multi-layer perceptron neural network. It is shown that the ROM based network is considerably simpler than the RAM based network, at the expense of a dramatically increased time to update the weights during training.

Citation Download Citation

Philip B. James-Roxby and Brandon J. Blodget "High-performance reconfigurable constant coefficient multiplier implementations", Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); https://doi.org/10.1117/12.402519

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