Programming method and a management unit in a reconfigurable processor with cell-array structure for general-purpose calculation

Takayuki Morishita; Kiyotaka Komoku; Fumihiro Hatano; Iwao Teramoto

doi:10.1117/12.402522

6 October 2000 Programming method and a management unit in a reconfigurable processor with cell-array structure for general-purpose calculation

Takayuki Morishita, Kiyotaka Komoku, Fumihiro Hatano, Iwao Teramoto

Author Affiliations +

Proceedings Volume 4212, Reconfigurable Technology: FPGAs for Computing and Applications II; (2000) https://doi.org/10.1117/12.402522
Event: Information Technologies 2000, 2000, Boston, MA, United States

Abstract

We have been developing a parallel processor that it is possible to reconfigure to realize a general-purpose computation at very high speed. Dynamic Reconfiguration means to change a kind of and a number of processing elements and connection between processing elements at real time. This function realizes the optimum hardware to execute any software and decrease a scale of hardware to execute software. Our proposed processor is configured with cells, which make any kind of processing, and bus, which makes any routing between cells. We support reconfiguration based on very larger macro cell than a logic cell in this processor. Decreasing a command length by using macro cell is responsible for realizing a dynamically reconfiguration. We improve a usage of sources by separating cells as four kind parts, i.e., an arithmetic calculation cell, a logic calculation cell, a memory cell and a counter cell. This processor can be programmed by two kinds of method, i.e., both circuit design and c language programming. In this paper, we extend circuit design technique to describing a dynamically reconfiguration of circuit component and propose a management unit in reconfigurable processor necessary for executing a program. Finally, we examine a performance of this processor by using an example program.

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Takayuki Morishita, Kiyotaka Komoku, Fumihiro Hatano, and Iwao Teramoto "Programming method and a management unit in a reconfigurable processor with cell-array structure for general-purpose calculation", Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); https://doi.org/10.1117/12.402522

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