FPGA architecture for a videowall image processor

Alessandro Skarabot; Giovanni Ramponi; Luigi Buriola

doi:10.1117/12.424964

8 May 2001 FPGA architecture for a videowall image processor

Alessandro Skarabot, Giovanni Ramponi, Luigi Buriola

Proceedings Volume 4304, Nonlinear Image Processing and Pattern Analysis XII; (2001) https://doi.org/10.1117/12.424964
Event: Photonics West 2001 - Electronic Imaging, 2001, San Jose, CA, United States

Abstract

This paper proposes an FPGA architecture for a videowall image processor. To create a videowall, a set of high resolution displays is arranged in order to present a single large image or smaller multiple images. An image processor is needed to perform the appropriate format conversion corresponding to the required output configuration, and to properly enhance the image contrast. Input signals either in the interlaced or in the progressive format must be managed. The image processor we propose is integrated into two different blocks: the first one implements the deinterlacing task for a YCbCr input video signal, then it converts the progressive YCbCr to the RGB data format and performs the optional contrast enhancement; the other one performs the format conversion of the RGB data format. Motion-adaptive vertico-temporal deinterlacing is used for the luminance signal Y; the color difference signals Cb and Cr instead are processed by means of line average deinterlacing. Image contrast enhancement is achieved via a modified Unsharp Masking technique and involves only the luminance Y. The format conversion algorithm is the bilinear interpolation technique employing the Warped Distance approach and is performed on the RGB data. Two different subblocks have been considered in the system architecture since the interpolation is performed column-wise and successively row- wise.

Citation Download Citation

Alessandro Skarabot, Giovanni Ramponi, and Luigi Buriola "FPGA architecture for a videowall image processor", Proc. SPIE 4304, Nonlinear Image Processing and Pattern Analysis XII, (8 May 2001); https://doi.org/10.1117/12.424964

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