A One Gigaflop VLSI Systolic Processor

John H. Avila; Philip J. Kuekes

doi:10.1117/12.936454

28 November 1983 A One Gigaflop VLSI Systolic Processor

John H. Avila, Philip J. Kuekes

Proceedings Volume 0431, Real-Time Signal Processing VI; (1983) https://doi.org/10.1117/12.936454
Event: 27th Annual Technical Symposium, 1983, San Diego, United States

Abstract

Inexpensive, efficient VLSI circuits combined with a highly parallel systolic architecture will allow the construction of one gigaflop linear algebra processors for signal processing. This paper presents some results in increasing the efficiency of such processors to 100%.

Citation Download Citation

John H. Avila and Philip J. Kuekes "A One Gigaflop VLSI Systolic Processor", Proc. SPIE 0431, Real-Time Signal Processing VI, (28 November 1983); https://doi.org/10.1117/12.936454

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