Methodology of a short-loop yield analysis for defect impact studies

Andrew Skumanich; Elmira Ryabova

doi:10.1117/12.425268

23 April 2001 Methodology of a short-loop yield analysis for defect impact studies

Andrew Skumanich, Elmira Ryabova

Proceedings Volume 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II; (2001) https://doi.org/10.1117/12.425268
Event: Microelectronic and MEMS Technologies, 2001, Edinburgh, United Kingdom

Abstract

A methodology is described which establishes the prioritization of defects based on electrical impact of the different defect types using a Short Loop Yield Monitor under conditions of low statistics. Probe results from specifically designed test patterns for interconnect structures are correlated with optical defect inspection data to determine the kill rates of various defects. The results provide quantitative means to rank the importance of defects as well as the effectiveness of the inspection strategy. The wafers are optically inspected at each process step and reviewed with an automated SEM (SEMVision). The defects are tracked and a defect Pareto is established. After final processing, the electrical testing is performed and correlations are established. The defects are ranked by a quantitative approach based on the kill rate. A unique and important feature of the approach is to use deliberately introduced defects to study the impact at specific process points. The use of controlled defect introduction allows an improved statistical analysis for low coverage inspection plans. It appears that particles that occur at early stages in the process have an enhanced impact because of a potential size amplification effect. With the impact quantified, effective inspection and defect reduction plans can be implemented.

Citation Download Citation

Andrew Skumanich and Elmira Ryabova "Methodology of a short-loop yield analysis for defect impact studies", Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001); https://doi.org/10.1117/12.425268

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