Verifying RET mask layouts

Jeffrey P. Mayhew; Michael L. Rieger; Jiangwei Li; Lin Zhang; Zongwu Tang; James P. Shiely

doi:10.1117/12.475670

12 July 2002 Verifying RET mask layouts

Jeffrey P. Mayhew, Michael L. Rieger, Jiangwei Li, Lin Zhang, Zongwu Tang, James P. Shiely

Proceedings Volume 4692, Design, Process Integration, and Characterization for Microelectronics; (2002) https://doi.org/10.1117/12.475670
Event: Design, Process Integration, and Characterization for Microelectronics, 2002, Santa Clara, CA, United States

Abstract

Mask layouts with reticle enhancement techniques (RET) - including optical proximity correction (OPC), phase shift mask (PSM), Off-axis illumination, assist features (AF) - no longer closely resemble the design or wafer layouts. RET techniques are also applied with varying degrees of rigor to different portions of the layout, to constrain overall mask complexity while maintaining design requirements in critical areas. These factors make verifying RET mask layouts much more challenging. The simulation-based verification principle is straightforward: a wafer layout is simulated from the RET mask layout and compared to the intended design layout or 'target'. The required simulation technologies are mature and available today in commercial tools capable of handling large data files. The challenge in efficient verification is to establish comprehensive required for sub- wavelength lithography. Today, some simple criteria are inferred from the design or lithographic effects. Ideally, more specific information related to design 'intent' and tolerances should be built into the physical design for use in RET synthesis and verification, as well as in circuit and timing analysis. In this paper we explore emerging RET verification strategies that offer a high degree of flexibility and programmability. We will also illustrate how these techniques can take advantage of 'design intent' information embedded in the physical design, resulting in robust verification that is not confused by the complex tradeoffs required for today's sophisticated RET methodologies.

Citation Download Citation

Jeffrey P. Mayhew, Michael L. Rieger, Jiangwei Li, Lin Zhang, Zongwu Tang, and James P. Shiely "Verifying RET mask layouts", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); https://doi.org/10.1117/12.475670

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available