Real-time hardware architectures for the bi-orthogonal wavelet transform

Greg Knowles

doi:10.1117/12.477481

14 April 2003 Real-time hardware architectures for the bi-orthogonal wavelet transform

Greg Knowles

Proceedings Volume 5012, Real-Time Imaging VII; (2003) https://doi.org/10.1117/12.477481
Event: Electronic Imaging 2003, 2003, Santa Clara, CA, United States

Abstract

In this note we give a new architecture for the bi-orthogonal wavelet transform. The basis of our approach is a new convolver circuit that generates low and high pass values simultaneously in the forward transform, and combines low and high pass values in the inverse transform to produce even and odd data values. This is possible because of the symmetry of the bi-orthogonal wavelet coefficients and because the bi-orthogonal wavelet transform preserves the number of input data samples. The results are optimal in the sense of the number of multipliers used. The architecture given here is more efficient than lifting, for example in the case of the Daubechies 9-7 wavelet, lifting requires 6 multiplications per transformed (H, G) pair, while this method uses only 5. Note that the designs given here are fully pipelined and so are suitable for high-speed or low-power implementation.

Citation Download Citation

Greg Knowles "Real-time hardware architectures for the bi-orthogonal wavelet transform", Proc. SPIE 5012, Real-Time Imaging VII, (14 April 2003); https://doi.org/10.1117/12.477481

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