157-nm lithography for 65-nm node SRAM-gate

Toshifumi Suganaga; Shigeo Irie; Seiro Miyoshi; Jae-Hwan Kim; Kunio Watanabe; Eiji Kurose; Takamitsu Furukawa; Takuya Hagiwara; Toshiyuki Ishimaru; Toshiro Itani

doi:10.1117/12.485376

26 June 2003 157-nm lithography for 65-nm node SRAM-gate

Toshifumi Suganaga, Shigeo Irie, Seiro Miyoshi, Jae-Hwan Kim, Kunio Watanabe, Eiji Kurose, Takamitsu Furukawa, Takuya Hagiwara, Toshiyuki Ishimaru, Toshiro Itani

Author Affiliations +

Proceedings Volume 5040, Optical Microlithography XVI; (2003) https://doi.org/10.1117/12.485376
Event: Microlithography 2003, 2003, Santa Clara, California, United States

Abstract

We evaluated the requirements for 65-nm SRAM gate fabrication using attenuated phase shifting masks (att-PSM). Off-axis illumination (OAI) and att-PSM, together with optical proximity correction (OPC) were used as resolution enhancement techniques (RETs) for ultimate resolution. It was shown that the photolithographic parameters of the transmittance of the att-PSM and the illumination conditions for optimum conditions were a transmittance of between 15 and 20% and 3/4 annular illumination. The exposure latitude was simulated to be more than 10.9% at 300-nm defocus for a critical dimension (CD) specification of 10%. It has been demonstrated that a 65-nm SRAM-gate, with a line and space (L/S) ratio limited to 1:2 at the minimum pitch, could be fabricated with sufficient depth of focus (DOF). The pattern transfer was accomplished with a bi-layer process, in which the reactive ion etching (RIE) selectivity between a silicon-containing resist and an organic film is very high. This bi-layer process enabled the application of a very thin resist layer. The conditions described in this paper proved successful for the fabrication of a 65-nm SRAM gate with a good pattern profile despite the resist thickness of less than 120nm.

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Toshifumi Suganaga, Shigeo Irie, Seiro Miyoshi, Jae-Hwan Kim, Kunio Watanabe, Eiji Kurose, Takamitsu Furukawa, Takuya Hagiwara, Toshiyuki Ishimaru, and Toshiro Itani "157-nm lithography for 65-nm node SRAM-gate", Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); https://doi.org/10.1117/12.485376

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