High-speed clock recovery unit based on a phase aligner

Efrain Tejera; Roberto Esper-Chain; Felix Tobajas; Valentin De Armas; Roberto Sarmiento

doi:10.1117/12.498653

21 April 2003 High-speed clock recovery unit based on a phase aligner

Efrain Tejera, Roberto Esper-Chain, Felix Tobajas, Valentin De Armas, Roberto Sarmiento

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498653
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference clock running at the nominal frequency of the received signal. This high speed reference clock is generated using a crystal and a clock multiplier unit. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45 degrees between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. This performances make this design suitable for systems such as high speed serial link technologies. This system has been designed for CMOS 0.25μm at 1.25GHz and has been verified through HSpice simulations.

Citation Download Citation

Efrain Tejera, Roberto Esper-Chain, Felix Tobajas, Valentin De Armas, and Roberto Sarmiento "High-speed clock recovery unit based on a phase aligner", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498653

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KEYWORDS

Clocks

Sensors

Control systems

Analog electronics

Signal detection

Logic

Tolerancing

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