Low-power high-performance 2D transform coprocessor for H.264 video compression standard

Philip P. Dang

doi:10.1117/12.527227

19 April 2004 Low-power high-performance 2D transform coprocessor for H.264 video compression standard

Philip P. Dang

Proceedings Volume 5309, Embedded Processors for Multimedia and Communications; (2004) https://doi.org/10.1117/12.527227
Event: Electronic Imaging 2004, 2004, San Jose, California, United States

Abstract

This paper presents a VLSI architecture and an efficient implementation of an embedded transform coprocessor for H.264 video compression standard. The proposed coprocessor was designed to work with an ARM946E-S processor. To enhance the performance, both data parallelism and pipelined architecture are utilized in the design. In this study, coprocessor was synthesized with 0.18 μm CMOS technology and its footprint is only 0.0838 mm². Coprocessor can calculate 2-D transform for a macroblock in 30 clock cycles. The 2-D transform coprocessor dissipates 529 μW with 1.55-volt power supply at 10 MHz clock rate.

Citation Download Citation

Philip P. Dang "Low-power high-performance 2D transform coprocessor for H.264 video compression standard", Proc. SPIE 5309, Embedded Processors for Multimedia and Communications, (19 April 2004); https://doi.org/10.1117/12.527227

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available