Optimization of scatterometry parameters for the gate level of the 90 nm node

Philippe Leray; Shaunee Cheng

doi:10.1117/12.610664

10 May 2005 Optimization of scatterometry parameters for the gate level of the 90 nm node

Philippe Leray, Shaunee Cheng

Proceedings Volume 5752, Metrology, Inspection, and Process Control for Microlithography XIX; (2005) https://doi.org/10.1117/12.610664
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

In recent years scatterometry has been shown to have impressive long term repeatability of better than 1.5nm for simple resist stacks. Equally impressive results have been reported for Shallow Trench Isolation (STI), thus enabling effective monitoring of STI trench etch. These results were achieved by following the methodology that results obtained for a given library must be rigorously tested, to ensure measured results respond correctly to process variation. Following the same methodology, the scatterometry capability for the gate stack after litho and after etch has been evaluated. The stack used is IMEC's standard gate process for the 90 nm node. After a complete library generation, these results are compared to CD SEM and X SEM. These optimized libraries are used on few wafers with strong etch variations. The response to process variations is shown. A method to qualify and monitor the etch tool is demonstrated.

Citation Download Citation

Philippe Leray and Shaunee Cheng "Optimization of scatterometry parameters for the gate level of the 90 nm node", Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); https://doi.org/10.1117/12.610664

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