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Functional validation plays an important role in the design cycle of digital integrated circuits. The generation of good test benches is required for checking the complete circuit behaviour. Early location of design errors could highly reduce the development time and cost for these circuits. There are several initiatives for the development of methods that enhance the functional validation of a design. Traditionally, logic abstraction level has been most employed for this purpose, but recent years have shown a strong trend to treat the problem at higher abstraction levels, where design teams normally work. High abstraction levels and automatic synthesis tools are currently being used in top-down methodology. These aspects make difficult to find out design errors when the circuit is described in lower levels of abstraction. It is crucial to obtain a complete functional validation system applicable in the first design stages, where circuits are currently being designed, and also usable along the whole design process for further test plans.
In this paper we propose a complete methodology for performing high quality functional validation. The proposed method checks the capability of a given test bench to detect design errors in a circuit description. This checking employs functional simulation of the circuit description at RT level together with the application of error models. An automatic and formal protocol has been developed so that design teams could apply it with no extra effort. The method provides a measurement of the quality of functional validation as well as the location of non-enough validated areas in the circuit.
Therefore, the proposed method helps designers in the process of performing the functional validation of their circuits, which could be applied automatically from RT descriptions to lower abstraction levels. Finally, experimental results have proved the correctness of the proposed method as well as the error models applied.
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