An RNS public key cryptography accelerator

Tom A. Coleman; James A. Kitchener; David L. Pudney; Kelvin D. Wauchope; Braden J. Phillips

doi:10.1117/12.695962

11 January 2007 An RNS public key cryptography accelerator

Tom A. Coleman, James A. Kitchener, David L. Pudney, Kelvin D. Wauchope, Braden J. Phillips

Proceedings Volume 6414, Smart Structures, Devices, and Systems III; 641422 (2007) https://doi.org/10.1117/12.695962
Event: SPIE Smart Materials, Nano- and Micro-Smart Systems, 2006, Adelaide, Australia

Abstract

A new design of a hardware accelerator for RSA cryptography is described. The accelerator performs long integer (1024-bit) modular exponentiation using the Residue Number System (RNS). It is implemented on an FPGA and interfaced to a host PC via the PCI bus. The accelerator uses the RNS to break the long operands into short channels that are processed in parallel. The performance of this architecture is evaluated and the potential for its further improvement is discussed.

Citation Download Citation

Tom A. Coleman, James A. Kitchener, David L. Pudney, Kelvin D. Wauchope, and Braden J. Phillips "An RNS public key cryptography accelerator", Proc. SPIE 6414, Smart Structures, Devices, and Systems III, 641422 (11 January 2007); https://doi.org/10.1117/12.695962

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