Post exposure bake unit equipped with wafer-shape compensation technology

Shigehiro Goto; Akihiko Morita; Kenichi Oyama; Shimpei Hori; Keiji Matsuchika; Hideyuki Taniguchi

doi:10.1117/12.711095

26 March 2007 Post exposure bake unit equipped with wafer-shape compensation technology

Shigehiro Goto, Akihiko Morita, Kenichi Oyama, Shimpei Hori, Keiji Matsuchika, Hideyuki Taniguchi

Proceedings Volume 6519, Advances in Resist Materials and Processing Technology XXIV; 651937 (2007) https://doi.org/10.1117/12.711095
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Citation Download Citation

Shigehiro Goto, Akihiko Morita, Kenichi Oyama, Shimpei Hori, Keiji Matsuchika, and Hideyuki Taniguchi "Post exposure bake unit equipped with wafer-shape compensation technology", Proc. SPIE 6519, Advances in Resist Materials and Processing Technology XXIV, 651937 (26 March 2007); https://doi.org/10.1117/12.711095

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
8 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Semiconducting wafers

Temperature metrology

Critical dimension metrology

Oxides

Optical lithography

Silicon

Silicon films

Show All Keywords

Keywords/Phrases

Search In:

Publication Years